NC

Q1

Q1 VCCO

Q5

Q5

VCCO

NC

LEN1

LEN2

MR

LOGIC DIAGRAM

D5

D4

D3

VEE

D2

D1

D0

26

27

28

2

3

4

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

5

6

7

8

9

10

Q4

Q4

VCC

Q3

Q3

Q2

Q2

VCCO Q0

Q0

D0

D1

D2

D3

D4

D5

LEN1

LEN2

MR

Q0

Q0

Q1

Q1

Q2

Q2

Q3

Q3

Q4

Q4

Q5

Q5

D

R

D

R

D

R

D

R

D

R

D

R

1

Pinout: 28-Lead PLCC (Top View)

* All VCC and VCCO pins are tied together on the die.

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

2–1

REV 2

12/93

6Bit D Latch

The MC10E/100E150 contains six D-type latches with differential

outputs. When both Latch Enables (LEN1, LEN2) are LOW, the latch is

transparent and input data transitions propagate through to the output. A

logic HIGH on either LEN1 or LEN2 (or both) latches the data. The Master

Reset (MR) overrides all other controls to set the Q outputs low.

PIN NAMES

Pin

Function

D0 – D5

Data Inputs

LEN1, LEN2

Latch Enables

MR

Master Reset

Q0 – Q5

True Outputs

Q0 – Q5

Inverting Outputs

MC10E150

MC100E150

6-BIT D LATCH

FN SUFFIX

PLASTIC PACKAGE

CASE 776-02