MC10E197

MOTOROLA

ECLinPS and ECLinPS Lite

DL140 — Rev 4

2–2

Pinout: 28-Lead PLCC (Top View)

25

24

23

22

21

20

19

18

17

16

15

14

13

12

5

6

7

8

9

10

11

26

27

28

2

3

4

RDCLK

RDCLK

VCC

RSDATA

RSDATA

PUMPUP

RSETDN

TEST

EXTVCO

ENVCO

VEE

ACQ

TYPE

RDEN

1

PIN DESCRIPTIONS

REFCLK

Reference clock equivalent to one clock cycle per decoding window.

RDEN

Enable data synchronizer when HIGH. When LOW enable the phase/frequency detector steered by REFCLK.

RAWD

Data Input to Synchronizer logic.

VCOIN

VCO control voltage input

CAP1/CAP2

VCO frequency controlling capacitor inputs

ENVCO

VCO select pin. LOW selects the internal VCO and HIGH selects the external VCO input. Pin floats LOW when left open.

EXTVCO

External VCO pin selected when ENVCO is HIGH

ACQ

Acquisition circuitry select pin. This pin must be driven HIGH at the end of the data sync field for some sync field types.

TYPE

Selects between the two types of commonly used sync fields. When LOW it selects a sync field interspersed with 3 zeroes

(2:7 RLL code). When HIGH it selects a sync field interspersed with 2 zeroes (1:7 RLL code).

TEST

Input included to initialize the clock flip-flop for test purposes only. Pin should be left open (LOW) in actual application.

PUMPUP

Open collector charge pump output for the signal pump

PUMPDN

Open collector charge pump output for the reference pump

RSETUP

Current setting resistor for the signal pump

RSETDN

Current setting resistor for the reference pump

RDATA

Synchronized data output

RDCLK

Synchronized clock output

VCC, VCCO,

VCCVCO

Most positive supply rails. Digital and analog supplies are independent on chip

VEE, VEEVCO

Most negative supply rails. Digital and analog supplies are independent on chip