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CS4361-CZZ Datenblatt(PDF) 9 Page - Cirrus Logic |
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CS4361-CZZ Datenblatt(HTML) 9 Page - Cirrus Logic |
9 / 23 page CS4361 DS672A2 9 SWITCHING CHARACTERISTICS - SERIAL AUDIO INTERFACE Notes: 11. Not all sample rates are supported for all clock ratios. See table “Common Clock Frequencies” on page 12 for supported ratios and frequencies. 12. In Internal SCLK Mode, the duty cycle must be 50% ± 1/2 MCLK period. 13. The SCLK / LRCK ratio may be either 32, 48, 64, or 72. This ratio depends on data format and MCLK/LRCK ratio. (See figures 7-10) Parameters Symbol Min Typ Max Units MCLK Frequency 0.512 - 50 MHz MCLK Duty Cycle 45 - 55 % Input Sample Rate All MCLK/LRCK ratios combined (Note 11) 256x, 384x, 1024x 256x, 384x 512x, 768x 1152x 128x, 192x 64x, 96x 128x, 192x Fs 2 2 84 42 30 50 100 168 216 54 134 67 34 108 216 216 kHz kHz kHz kHz kHz kHz kHz kHz External SCLK Mode LRCK Duty Cycle (External SCLK only) 45 50 55 % SCLK Pulse Width Low tsclkl 20 - - ns SCLK Pulse Width High tsclkh 20 - - ns SCLK Duty Cycle 45 50 55 % SCLK rising to LRCK edge delay tslrd 20 - - ns SCLK rising to LRCK edge setup time tslrs 20 - - ns SDIN valid to SCLK rising setup time tsdlrs 20 - - ns SCLK rising to SDIN hold time tsdh 20 - - ns Internal SCLK Mode LRCK Duty Cycle (Internal SCLK only) (Note 12) - 50 - % SCLK Period (Note 13) tsclkw -- ns SCLK rising to LRCK edge tsclkr -- µs SDIN valid to SCLK rising setup time tsdlrs -- ns SCLK rising to SDIN hold time MCLK / LRCK =1152, 1024, 512, 256, 128, or 64 tsdh -- ns SCLK rising to SDIN hold time MCLK / LRCK = 768, 384, 192, or 96 tsdh -- ns 109 SCLK ----------------- tsclkw 2 ------------------ 109 512 ()Fs ----------------------10 + 109 512 ()Fs ----------------------15 + 109 384 ()Fs ----------------------15 + |
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