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CDB44800 Datenblatt(PDF) 5 Page - Cirrus Logic

Teilenummer CDB44800
Bauteilbeschribung  6-Channel Digital Amplifier Controller
Download  78 Pages
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Hersteller  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CDB44800 Datenblatt(HTML) 5 Page - Cirrus Logic

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DS633PP1
5
CS44600
7.19.1 Channel Compensation Filter - Fine Adjust (CHXX_FINE[5:0]) ........................ 61
7.20 Interrupt Mode Control (address 28h) ........................................................................... 61
7.20.1 Interrupt Pin Control (INT1/INT0) ...................................................................... 61
7.20.2 Overflow Level/Edge Select (OVFL_L/E) .......................................................... 62
7.21 Interrupt Mask (address 29h) ........................................................................................ 62
7.22 Interrupt Status (address 2Ah) (Read Only) ................................................................. 62
7.22.1 SRC Unlock Interrupt (SRC_UNLOCK) ............................................................ 62
7.22.2 SRC Lock Interrupt (SRC_LOCK) ..................................................................... 63
7.22.3 Ramp-Up Complete Interrupt (RMPUP_DONE) ............................................... 63
7.22.4 Ramp-Down Complete Interrupt (RMPDN_DONE) .......................................... 63
7.22.5 Mute Complete Interrupt (Mute_DONE) ........................................................... 63
7.22.6 Channel Over Flow Interrupt (OVFL_INT) ........................................................ 63
7.22.7 GPIO Interrupt Condition (GPIO_INT) .............................................................. 63
7.23 Channel Over Flow Status (address 2Bh) (Read Only) ................................................. 64
7.23.1 ChXX_OVFL ..................................................................................................... 64
7.24 GPIO Pin In/Out (address 2Ch) ..................................................................................... 64
7.24.1 GPIO In/Out Selection (GPIOX_I/O) ................................................................. 64
7.25 GPIO Pin Polarity/Type (address 2Dh) .......................................................................... 64
7.25.1 GPIO Polarity/Type Selection (GPIOX_P/T) ..................................................... 64
7.26 GPIO Pin Level/Edge Trigger (address 2Eh) ................................................................. 65
7.26.1 GPIO Level/Edge Input Sensitive (GPIOX_L/E) ............................................... 65
7.27 GPIO Status Register (address 2Fh) ............................................................................. 65
7.27.1 GPIO Pin Status (GPIOX_STATUS) ................................................................. 65
7.28 GPIO Interrupt Mask Register (address 30h) ................................................................ 66
7.28.1 GPIO Pin Interrupt Mask (M_GPIOX) ............................................................... 66
7.29 PWM Configuration Register (address 31h) ................................................................. 66
7.29.1 Over Sample Rate Selection (OSRATE) .......................................................... 66
7.29.2 Channels A1 and B1 Output Configuration (A1/B1_OUT_CNFG) .................... 66
7.29.3 Channels A2 and B2 Output Configuration (A2/B2_OUT_CNFG) .................... 66
7.29.4 Channel A3 Output Configuration (A3_OUT_CNFG) ....................................... 67
7.29.5 Channel B3 Output Configuration (B3_OUT_CNFG) ....................................... 67
7.30 PWM Minimum Pulse Width Register (address 32h) .................................................... 67
7.30.1 Disable PWMOUTXX - Signal (DISABLE_PWMOUTXX-) ................................ 67
7.30.2 Minimum PWM Output Pulse Settings (MIN_PULSE[4:0]) ............................... 67
7.31 PWMOUT Delay Register (address 33h) ...................................................................... 68
7.31.1 Differential Signal Delay (DIFF_DLY[2:0]) ........................................................ 68
7.31.2 Channel Delay Settings (CHNL_DLY[4:0]) ...................................................... 68
7.32 PSR and Power Supply Configuration (address 34h) .................................................... 69
7.32.1 Power Supply Rejection Enable (PSR_EN) ...................................................... 69
7.32.2 Power Supply Rejection Reset (PSR_RESET) ................................................. 70
7.32.3 Power Supply Rejection Feedback Enable (FEEDBACK_EN) ......................... 70
7.32.4 Power Supply Sync Clock Divider Settings (PS_SYNC_DIV[2:0]) ................... 70
7.33 Decimator Shift/Scale (addresses 35h, 36h, 37h) ......................................................... 70
7.33.1 Decimator Shift (DEC_SHIFT[2:0]) ................................................................... 70
7.33.2 Decimator Scale (DEC_SCALE[18:0]) .............................................................. 71
7.34 Decimator Outd (addresses 3Bh, 3Ch, 3Dh) ................................................................. 71
7.34.1 Decimator Outd (DEC_OUTD[23:0]) ................................................................. 71
8. PARAMETER DEFINITIONS .................................................................................................. 72
9. REFERENCES ........................................................................................................................ 74
10. PACKAGE DIMENSIONS
........................................................................................... 75
11. THERMAL CHARACTERISTICS ......................................................................................... 76
12. REVISION HISTORY ............................................................................................................ 77


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