CS61305A-IP1 datasheet(5/44 Pages) CIRRUS

Teilenummer	CS61305A-IP1

Bauteilbeschribung	T1/E1 LINE INTERFACE

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Hersteller	CIRRUS [Cirrus Logic]

Direct Link	http://www.cirrus.com

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T1 SWITCHING CHARACTERISTICS (TA = -40°C to 85°C; TV+, RV+ = 5.0V ±5%;

GND = 0V; Inputs: Logic 0 = 0V, Logic 1 = RV+; See Figures 1, 2, & 3)

Parameter

Symbol

Min

Typ

Max

Units

Crystal Frequency

(Note 23)

fc

-

6.176000

-

MHz

ACLKI Duty Cycle

tpwh3/tpw3

40

-

60

%

ACLKI Frequency

(Note 24)

faclki

-

1.544

-

MHz

RCLK Cycle Width

(Note 25)

tpw1

tpwh1

tpwl1

320

130

100

648

190

458

980

240

850

ns

Rise Time, All Digital Outputs

(Note 26)

tr

-

85

ns

Fall Time, All Digital Outputs

(Note 26)

tf

-

85

ns

TCLK Frequency

ftclk

-

1.544

-

MHz

TCLK Pulse Width

(Notes 16, 27, 28)

(Notes 29, 30)

tpwh2

80

150

-

500

ns

TPOS/TNEG (TDATA) to TCLK Falling Setup Time

tsu2

25

-

ns

TCLK Falling to TPOS/TNEG (TDATA) Hold Time

th2

25

-

ns

RPOS/RNEG Valid Before RCLK Falling

(Note 27)

tsu1

150

274

-

ns

RDATA Valid Before RCLK Falling

(Note 29)

tsu1

150

274

-

ns

RPOS/RNEG Valid Before RCLK Rising

(Note 28)

tsu1

150

274

-

ns

RPOS/RNEG Valid After RCLK Falling

(Note 27)

th1

150

274

-

ns

RDATA Valid After RCLK Falling

(Note 29)

th1

150

274

-

ns

RPOS/RNEG Valid After RCLK Rising

(Note 28)

th1

150

274

-

ns

Notes: 23. Crystal must meet specifications described in CXT6176/CXT8192 data sheet.

24. ACLKI provided by an external source or TCLK but not RCLK.

25. RCLK duty cycle will vary with extent by which pulses are displaced by jitter. Specified under worst

case jitter conditions: 0.4 UI AMI data displacement for T1 and 0.2 UI AMI data displacement for E1.

26. At max load of 1.6 mA and 50 pF.

27. Host Mode (CLKE = 1).

28. Hardware Mode, or Host Mode (CLKE = 0).

29. Extended Hardware Mode.

30. The maximum TCLK burst rate is 5 MHz and tpw2 (min) = 200ns. The maximum gap size that can

be tolerated on TCLK is 138 VI.

CS61305A

DS157PP3

5

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