FAN6520A datasheet(10/15 Pages) FAIRCHILD

Teilenummer	FAN6520A

Bauteilbeschribung	Single Synchronous Buck PWM Controller

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Hersteller	FAIRCHILD [Fairchild Semiconductor]

Direct Link	http://www.fairchildsemi.com

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10 / 15 page

10

REV. 1.0.2 8/26/04

FAN6520A

PRODUCT SPECIFICATION

RMS current required by the circuit. The capacitor voltage

rating should be at least 1.25 times greater than the maxi-

mum input voltage and a voltage rating of 1.5 times is a

conservative guideline.

The RMS current rating requirement (IRMS) for the input

capacitor of a buck regulator is:

where the converter duty cycle;

. For a

through-hole design, several electrolytic capacitors may be

needed. For surface-mount designs, solid tantalum capaci-

tors can be used, but caution must be exercised with regard

to the capacitor’s surge current rating. The capacitors must

be capable of handling the surge current at power-up. Some

capacitor series available from reputable manufacturers are

surge current tested.

Bootstrap Circuit

The bootstrap circuit uses a charge storage capacitor

(CBOOT) and the internal diode, as shown in Figure 1.

Selection of these components should be done after the

high-side MOSFET has been chosen. The required

capacitance is determined using the following equation:

where QG is the total gate charge of the high-side MOSFET,

and

∆VBOOT is the voltage droop allowed on the high-side

MOSFET drive. To prevent loss of gate drive, the bootstrap

capacitance should be at least 50 times greater than the CISS

of Q1.

Thermal Considerations

Total device dissipation:

PD = PQ + PHDRV + PLDRV

(4)

where PQ represents quiescent power dissipation:

PQ = VCC × [4mA + 0.036 (FSW – 100)]

(5)

where FSW is switching frequency (in kHz).

PHDRV represents internal power dissipation of the upper

FET driver.

PHDRV = PH(R) × PH(F)

(6)

Where PH(R) and PH(F) are internal dissipations for the

rising and falling edges respectively:

where:

PQ1 = QG1 × VGS(Q1) × FSW

(9)

Where QG1 is total gate charge of Q1 for its applied VGS.

As described in the equations above, the total power con-

sumed in driving the gate is divided in proportion to the

resistances in series with the MOSFET's internal gate node

as shown in Figure 9.

Figure 9. Driver Dissipation Model

RG is the polysilicon gate resistance, internal to the FET.

RE is the external gate drive resistor implemented in many

designs. Note that the introduction of RE can reduce driver

power dissipation, but excess RE may cause errors in the

“adaptive gate drive” circuitry. For more information

please refer to Fairchild app note AN-6003, “Shoot-through”

in Synchronous Buck Converters.

(http://www.fairchildsemi.com/an/AN/AN-6003.pdf)

PLDRV is dissipation of the lower FET driver.

PLDRV = PL(R) × PL(F)

(10)

Where PH(R) and PH(F) are internal dissipations for the rising

and falling edges, respectively:

where:

PQ2 = QG2 × VGS(Q2) × FSW

(13)

I

RMS

I

L

DD

2

–

()

=

(2)

D

V

OUT

V

IN

--------------

=

C

BOOT

Q

G

∆V

BOOT

----------------------

=

(3)

P

HR

()

P

Q1

R

HUP

R

HUP

R

E

R

G

++

-------------------------------------------

×

=

(7)

P

HF

()

P

Q1

R

HDN

R

HDN

R

E

R

G

++

--------------------------------------------

×

=

(8)

HDRV

Q1

G

R

G

RE

RHUP

BOOT

SW

R

HDN

S

P

LR

()

P

Q2

R

LUP

R

LUP

R

E

R

G

++

-------------------------------------------

×

=

(11)

P

LF

()

P

Q2

R

LDN

R

HDN

R

E

R

G

++

--------------------------------------------

×

=

(12)

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