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MC74ACT573NG Datenblatt(PDF) 2 Page - ON Semiconductor |
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MC74ACT573NG Datenblatt(HTML) 2 Page - ON Semiconductor |
2 / 12 page MC74AC573, MC74ACT573 http://onsemi.com 2 TRUTH TABLE Inputs Outputs OE LE Dn On L H H H L H L L L L X O0 H X X Z H = HIGH Voltage Level L = LOW Voltage Level Z = High Impedance X = Immaterial O0 = Previous O0 before LOW−to−HIGH Transition of Clock Functional Description The MC74AC573/74ACT574 contains eight D−type latches with 3−state output buffers. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW the latches store the information that was present on the D inputs a setup time preceding the HIGH−to−LOW transition of LE. The 3−state buffers are controlled by the Output Enable (OE) input. When OE is LOW, the buffers are enabled. When OE is HIGH the buffers are in the high impedance mode but this does not interfere with entering new data into the latches. Figure 3. Logic Diagram D LE Q D LE Q D LE Q D LE Q D LE Q D LE Q D LE Q D LE Q D1 D2 D3 D4 D5 D6 D7 LE OE O0 O1 O2 O3 O4 O5 O6 O7 D0 NOTE: That this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. |
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