MC74HC573A

http://onsemi.com

4

Guaranteed Limit

Symbol

Parameter

Test Conditions

VCC

V

– 55 to

25

_C

v 85_C

v 125_C

Unit

VOL

Maximum Low–Level Output

Voltage

Vout = 0.1 V or VCC – 0.1 V

|Iout| v 20 µA

2.0

4.5

6.0

0.1

0.1

0.1

0.1

0.1

0.1

0.1

0.1

0.1

V

Vin = VIH or VIL

|Iout| ≤ 2.4mA

|Iout| v 6.0 mA

|Iout| v 7.8 mA

3.0

4.5

6.0

0.26

0.26

0.26

0.33

0.33

0.33

0.4

0.4

0.4

Iin

Maximum Input Leakage

Current

Vin = VCC or GND

6.0

± 0.1

± 1.0

± 1.0

µA

IOZ

Maximum Three–State

Leakage Current

Output in High–Impedance State

Vin = VIL or VIH

Vout = VCC or GND

6.0

– 0.5

– 5.0

– 10

µA

ICC

Maximum Quiescent Supply

Current (per Package)

Vin = VCC or GND

IIoutI = 0 µA

6.0

4.0

40

160

µA

NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book

(DL129/D).

Guaranteed Limit

Symbol

Parameter

VCC

V

– 55 to

25

_C

v 85_C

v 125_C

Unit

tPLH,

tPHL

Maximum Propagation Delay, Input D to Q

(Figures 1 and 5)

2.0

3.0

4.5

6.0

150

100

30

26

190

140

38

33

225

180

45

38

ns

tPLH,

tPHL

Maximum Propagation Delay, Latch Enable to Q

(Figures 2 and 5)

2.0

3.0

4.5

6.0

160

105

32

27

200

145

40

34

240

190

48

41

ns

tPLZ,

tPHZ

Maximum Propagation Delay, Output Enable to Q

(Figures 3 and 6)

2.0

3.0

4.5

6.0

150

100

30

26

190

125

38

33

225

150

45

38

ns

tPZL,

tPZH

Maximum Propagation Delay, Output Enable to Q

(Figures 3 and 6)

2.0

3.0

4.5

6.0

150

100

30

26

190

125

38

33

225

150

45

38

ns

tTLH,

tTHL

Maximum Output Transition Time, Any Output

(Figures 1 and 5)

2.0

3.0

4.5

6.0

60

27

12

10

75

32

15

13

90

36

18

15

ns

Cin

Maximum Input Capacitance

10

10

10

pF

Cout

Maximum Three–State Output Capacitance (Output in High–Impedance

State)

15

15

15

pF

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON

Semiconductor High–Speed CMOS Data Book (DL129/D).

Typical @ 25

°C, VCC = 5.0 V

CPD

Power Dissipation Capacitance (Per Enabled Output)*

23

pF

* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the

ON Semiconductor High–Speed CMOS Data Book (DL129/D).