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TSC51C1XXX-A-12IBD Datenblatt(PDF) 8 Page - TEMIC Semiconductors

Teilenummer TSC51C1XXX-A-12IBD
Bauteilbeschribung  8-Bit Microcontroller for Digital Computer Monitors
Download  31 Pages
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Hersteller  TEMIC [TEMIC Semiconductors]
Direct Link  http://www.temic.de
Logo TEMIC - TEMIC Semiconductors

TSC51C1XXX-A-12IBD Datenblatt(HTML) 8 Page - TEMIC Semiconductors

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TSC8051C1
Rev. D (14 Jan. 97)
8
MATRA MHS
PORT 0 BIT
TO
LE
Q
WRITE
LATCH
MUX
LATCH
WRITE
LATCH
WRITE
TO
WRITE
TO
LATCH
TO
LATCH
READ
LATCH
MUX
PORT 1 BIT
DQ
P0.X
P0.X
PIN
VCC
CONTROL
ADDR/DATA
INT.
BUS
PIN
READ
LATCH
DQ
P1.X
LATCH
LE
Q
P1.X
PIN
VCC
CONTROL
PWMX
INT.
BUS
READ
PIN
INTERNAL
PULL–UP*
READ
LATCH
DQ
P2.X
LE
Q
P2.X
PIN
VCC
CONTROL
ADDR
INT.
BUS
READ
PIN
INTERNAL
PULL–UP
READ
LATCH
DQ
P3.X
LATCH
LE
Q
P3.X
PIN
VCC
SIO1
CONTROL*
INT.
BUS
ALTERNATE
OUTPUT
FUNCTION
* Internal pull–up not present on P3.6 and P3.7 when SIO1 is enabled.
ALTERNATE
INPUT
FUNCTION
READ
PIN
INTERNAL
PULL–UP*
READ
LATCH
PORT 2 BIT
PORT 3 BIT
MUX
* Internal pull–up not present on P1.0 to P1.3 when PWM8 to PWM11
are enabled
Figure 4. Port Bit Latches and I/O buffers
6.5. Reset Circuitry
The reset circuitry for the TSC8051C1 is connected to
the reset pin RST. A Schmitt trigger is used at the input
for noise rejection (see Figure 5. ).
A reset is accomplished by holding the RST pin high for
at least two machine cycles (24 oscillator periods) while
the oscillator is running. The CPU responds by
executing an internal reset. It also configures the ALE
and PSEN pins as inputs (they are quasi–bidirectional).
A Watchdog timer underflow if enabled, will force a
reset condition to the TSC8051C1 by an internal
connection.
The internal reset is executed during the second cycle in
which reset is high and is repeated every cycle until RST
goes low. It leaves the internal registers as follows:
Register
Content
ACC
00h
B
00h
DPTR
0000h
EICON
00h
HWDR
00h
IE
0X000000b
IP
XX000000b
MSCON
XXXXXXX0b
MXCR0–1
00h
P0–P3
FFh


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