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TLE75602-ESD Datenblatt(PDF) 61 Page - Infineon Technologies AG |
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TLE75602-ESD Datenblatt(HTML) 61 Page - Infineon Technologies AG |
61 / 70 page Datasheet 61 Rev. 1.0 2017-11-23 TLE75602-ESD SPIDER+ 12V Serial Peripheral Interface (SPI) 10.6.3 Register summary All registers with addresses not mentioned in Table 17 have to be considered as “reserved”. “Read” operations performed on those registers return the Standard Diagnosis. The column “Default” indicates the content of the register (8 bits) after a reset. DIAG_IOL n = 7 to 0 0010B 00B nr/w Open Load diagnostic current control bits DIAG_IOL.OUTn 0B (default) Diagnosis current not enabled 1B Diagnosis current enabled DIAG_OSM n = 7 to 0 0010B 01B nr Output Status Monitor bits DIAG_OSM.OUTn 0B (default) VDS> VDS(OL) (Low-Side channels and Auto- configurable used as Low-Side switches) or VOUT_S < VOUT_S(OL) (Auto-configurable used as High-Side switches) 1B VDS< VDS(OL) (Low-Side channels and Auto- configurable used as Low-Side switches) or VOUT_S > VOUT_S(OL) (Auto-configurable used as High-Side switches) HWCR 0011B 00B 8r/w Hardware Configuration Register bit HWCR.ACT (7) (Active Mode) 0B (default) Normal operation or device leaves Active Mode 1B Device enters Active Mode (see Chapter 6.1 for a description of the possible operative mode transitions) bit HWCR.RST (6) (Reset) 0B (default) Normal operation 1B Execute Reset command (self clearing) bits HWCR.PAR (3:0) (channels operating in parallel) 0B (default) Normal operation 1B two neighbour channels have Over Load and Over Temperature synchronized (see Chapter 7.3 for more details) bits 5:4 - reserved (default: 0B) HWCR_OCL n = 7 to 0 0011B 01B nw Output Clear Latch bits HWCR_OCL.OUTn 0B (default) Normal operation 1B Clear the error latch for the selected output Table 16 Register addressing space (cont’d) Register name ADDR0 ADDR1 Size Type Purpose |
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