IMX8MNIEC datasheet(60/89 Pages) NXP

Teilenummer	IMX8MNIEC

Bauteilbeschribung	i.MX 8M Nano Applications Processor Datasheet for Industrial Products

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i.MX 8M Nano Applications Processor Datasheet for Industrial Products, Rev. 0.1, 03/2020

60

NXP Semiconductors

Electrical characteristics

Figure 38. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3

3.9.9.2

FlexSPI output/write timing

The following sections describe output signal timing for the FlexSPI controller including control signals

and data outputs.

3.9.9.2.1

SDR mode

Figure 39. FlexSPI output timing in SDR mode

Table 51. FlexSPI output timing in SDR mode

Symbol

Parameter

Min.

Max.

Unit

—

[D:] Frequency of operation1

1 The actual maximum frequency supported is limited by the FlexSPIn_MCR0[RXCLKSRC] configuration used. See the

FlexSPI SDR input timing specifications.

TCSS and TCSH are configured by the FlexSPIn_FLSHAxCR1 register, the

default values are shown above. See the i.MX 8M Nano Applications

Processor Reference Manual (IMX8MNRM) for more details.

—166

MHz

TCK

[D:] SCK clock period

6.02

—

ns

TDSO

[D:] Output data setup time

2

—

ns

TDHO

[D:] Output data hold time

2

—

ns

TCSS

[D:] Chip select output setup time

3 x TCK - 1

—

ns

TCSH

[D:] Chip select output hold time

3 x TCK - 1

—

ns

TSCKD

TSCKDQS

SCK

SIO[0:7]

DQS

TCSS

TCK

TCSH

TDVO

TDHO

TDVO

TDHO

SCK

CS

SIO[0:7]

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