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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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BQ77904 Datenblatt(PDF) 21 Page - Texas Instruments |
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BQ77904 Datenblatt(HTML) 21 Page - Texas Instruments |
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21 / 46 page  0 V VSTATE_C SRP - SRN VSTATE_D PACK IS CHARGING PACK IS DISCHARGING Figure 8-5. State Comparator Thresholds 8.3.7 DSG FET Driver Operation The DSG pin is driven high only when no related faults (UV, OW, OTD, UTD, OCD1, OCD2, SCD, and CTRD are disabled) are present. It is a fast switching driver with a target on resistance of about 15–20 Ω and an off resistance of RDSGOFF. It is designed to allow users to select the optimized RGS value to archive the desirable FET rise and fall time per the application requirement and the choice of FET characteristics. When the DSG FET is turned off, the DSG pin drives low and all overcurrent protections (OCD1, OCD2, SCD) are disabled to better conserve power. These resume operation when the DSF FET is turned on. The device provides FET body diode protection through the state comparator if one FET driver is on and the other FET driver is off. The DSG driver may be turned on to prevent FET damage if the battery pack is charging while a discharge inhibit fault condition is present. This is done with the state comparator. The state comparator (with the VSTATE_C threshold) remains on for the entire duration of a DSG fault with no CHG fault event. • If (SRP-SRN) ≤ VSTATE_C and no charge event is detected, the DSG FET output will remain OFF due to the present of a DSG fault. • If (SRP-SRN) > VSTATE_C and a charge event is detected, the DSG FET output will turn ON for body diode protection. See the Section 8.3.6 section for details. The presence of any related faults, as shown in Figure 8-6, results in the DSGFET_OFF signal . DSGFET_OFF_UVn OWn DSGFET_OFF DSGFET_OFF_OCD1 DSGFET_OFF_OCD2 DSGFET_OFF_SCD DSGFET_OFF_UTD DSGFET_OFF_OTD CTRD Figure 8-6. Faults that Can Qualify DSGFET_OFF 8.3.8 CHG FET Driver Operation The CHG and CHGU pins are driven high only when no related faults (OV, OW, OTC, UTC, OTD, UTD, OCD1, OCD2, SCD, and CTRC are disabled) are present or the pack has a discharge current where (SRP-SRN) < VSTATE_D1 . The CHG pin drives the CHG FET, which is for use on the single device configuration or by the bottom device in a stack configuration. The CHGU pin has the same logic state as the CHG pin and is for use in the upper device (in a multi-stack configuration) to provide the drive signal to the CTRC pin of the lower device. The CHGU pin should never connect to the CHG FET directly. www.ti.com BQ77904, BQ77905 SLUSCM3K – APRIL 2020 – REVISED JULY 2020 Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: BQ77904 BQ77905 |
Ähnliche Teilenummer - BQ77904_V04 |
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Ähnliche Beschreibung - BQ77904_V04 |
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