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BQ79600-Q1 Datenblatt(PDF) 20 Page - Texas Instruments

Teilenummer BQ79600-Q1
Bauteilbeschribung  BQ79600-Q1 Automotive SPI/UART Communication Interface Functional-Safety Compliant With Automatic Host Wakeup
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SCLK
nCS
MOSI
MISO
SPI_RDY
SPI_RDY high indicates host
can read/write predefined
number of bytes
MSB_n
LSB_n
tSPI_CLKH
tSPI_CLKL
tSU
tH
t9
t10
t11
t12
t13
t14
tSPI_CLK
t>0
MSB_n+1
MSB_n
LSB_n
tH
Bit 7
Bit 0
MSB
LSB
One Byte
Bit 0
bit period = t
SPI_CLK
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 7
xxx
xxx
xxxx
xxxx
Hi or Low
Hi or Low
SPI_RDY may go low (and it is ok)
before finish read/write this batch
Figure 7-13. SPI Timing and Byte Definition
Note
Although SPI interface is full duplex at physical layer, at frame layer, it is effectively half duplex
because daisy chain only supports half duplex. It means, at the given time, only a command frame OR
a response frame is transmitted between MCU and the device.
• When command is being sent from MCU to the device, BQ79600 TX FIFO (2 buffers) should be
empty, 0xFF is sent to MCU (except in FIFO diagnostic mode)
• When response is being sent from device to MCU, MCU shall clock in 0xFF
• Host shall provide SPI clock in the range between 2MHz and 6MHz. This range is set by the predefined size
of FIFO. Even SPI can run at 6MHz, it does not increase the throughput of total system as daisy chain speed
still limit the throughput.
• To avoid collisions on the daisy chain interface, the MCU must wait until all expected response frames are
received (or waiting timer expires) before sending another command frame to bq79600. Refer to flow chart in
Figure 7-16.
• Master shall always drive MOSI to ‘1’ when not sending command frame into device.
• Host Read mode: from host perspective, read mode is between first byte of a valid read command and last
expected number of byte received.
• Device Read mode: start from first byte of a valid read command, device exists read mode when TX FIFO
times out and FIFO is empty. Device read mode is subset of host read mode. (concept used for
understanding of communication fault registers 0x2301, 0x2302)
• Other than Comm Clear, device rejects any data from MOSI before exiting Device Read mode.
• SPI module rejects any data from daisy chain (stack device) or from itself after TX FIFO timeout List item.
until it enters Device Read mode again.
BQ79600-Q1
SLUSDS1A – NOVEMBER 2019 – REVISED AUGUST 2020
www.ti.com
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