Datenblatt-Suchmaschine für elektronische Bauteile |
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BQ79600-Q1 Datenblatt(PDF) 22 Page - Texas Instruments |
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BQ79600-Q1 Datenblatt(HTML) 22 Page - Texas Instruments |
22 / 71 page 32 bytes RX FIFO BQ79600-Q1 Ping Buffer 128 bytes Daisy Chain Transceiver Pong Buffer 128 bytes TX FIFO MOSI MISO Aprox. 1Mbps Asynchronous COMH/COML Pins Aprox. 1Mbps Asynchronous Aprox. 1Mbps Asynchronous For simplicity, the drawing only shows dataflow from/to stack devices, it } •v[š •Z}Á šZ š(o}Á }( Œ (Œ}u / write to BQ79600 itself. SCLK: 2MHz - 6MHz Figure 7-15. SPI FIFO Simplified Diagram TX FIFO consists of two 128 bytes buffers (working together as Ping-Pong buffer). 1. When Ping buffer is filled up, Pong buffer should be empty, to store incoming data. 2. While Pong buffer is being filled, Ping buffer is being read. Each byte in buffer is reset to 0xFF once being read. Ping buffer shall be empty (read out) before Pong buffer is full. 3. After Pong buffer is filled up, Ping buffer catches up. 4. Device goes through this loop (step 1 to 3) till all response data are received. 5. Host has to read TX FIFO fast enough such that Ping (Pong) buffer is read out and ready to store data from daisy chain before Pong (Ping) buffer is full. Table 7-5. SPI_RDY Behavior Summary CASE # HI->LOW WHEN LO->HI WHEN a b Host Writes 1 In 2μs when RX FIFO has >= 16 bytes. After event a1, in 2μs when RX FIFO has < 8 bytes. Host Reads 2 In 5μs after device receives 1st byte of read command frame. In 1us after ping (pong) buffer is full. 3 TX buffer being read becomes empty (before transmitting out last bit of last byte in the buffer) Note: once going low, SPI_RDY remains low for 2μs no matter what. TX FIFO time out happened Note: TX FIFO timeout could happen while SPY_RDY is high (while host is reading TX FIFO), in this case, after event a3, SPI_RDY goes how for approximately 2μs, then come back high. Notes: • SPI_RDY sets flag only, doesn’t gate data flow into or out of device. • Once devices enters Device Read mode, device rejects any data from host other than COMM CLEAR. a1, b1 doesn’t apply anymore. • TX FIFO Timeout: after SPI module receives one byte of data from either daisy chain or BQ79600-Q1 local, a timer starts; this timer expires if there is no data received for 30μs. 7.3.2.1.2.2.2 Flow to Read/Write BQ79600-Q1 User shall follow flow chart Figure 7-16 to do read from device and Figure 7-17 to do write to device activities. BQ79600-Q1 SLUSDS1A – NOVEMBER 2019 – REVISED AUGUST 2020 www.ti.com 22 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: BQ79600-Q1 |
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Ähnliche Beschreibung - BQ79600-Q1_V01 |
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