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DRV8353M Datenblatt(PDF) 15 Page - Texas Instruments |
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DRV8353M Datenblatt(HTML) 15 Page - Texas Instruments |
15 / 76 page 12 SPI Timing Requirements at TA = –40°C to +125°C, VVM = 9 to 75 V (unless otherwise noted) MIN NOM MAX UNIT tREADY SPI ready after enable VM > UVLO, ENABLE = 3.3 V 1 ms tCLK SCLK minimum period 100 ns tCLKH SCLK minimum high time 50 ns tCLKL SCLK minimum low time 50 ns tSU_SDI SDI input data setup time 20 ns tH_SDI SDI input data hold time 30 ns tD_SDO SDO output data delay time SCLK high to SDO valid 30 ns tSU_nSCS nSCS input setup time 50 ns tH_nSCS nSCS input hold time 50 ns tHI_nSCS nSCS minimum high time before active low 400 ns tDIS_nSCS nSCS disable time nSCS high to SDO high impedance 10 ns www.ti.com DRV8353M SLVSFO2 – JULY 2020 Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: DRV8353M |
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