DRV8353M datasheet(16/76 Pages) TI

Teilenummer	DRV8353M

Bauteilbeschribung	DRV8353M 100-V Three-Phase Smart Gate Driver

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Hersteller	TI [Texas Instruments]

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13 Detailed Description

13.1 Overview

The DRV8353M family of devices are integrated 100-V gate drivers for three-phase motor drive applications.

These devices decrease system component count, cost, and complexity by integrating three independent half-

bridge gate drivers, charge pump and linear regulator for the high-side and low-side gate driver supply voltages,

optional triple current shunt amplifiers, and an optional 350-mA buck regulator. A standard serial peripheral

interface (SPI) provides a simple method for configuring the various device settings and reading fault diagnostic

information through an external controller. Alternatively, a hardware interface (H/W) option allows for configuring

the most commonly used settings through fixed external resistors.

The gate drivers support external N-channel high-side and low-side power MOSFETs and can drive up to 1-A

source, 2-A sink peak currents with a 25-mA average output current. The high-side gate drive supply voltage is

generated using a doubler charge-pump architecture that regulates the VCP output to VVDRAIN + 10.5-V. The

low-side gate drive supply voltage is generated using a linear regulator from the VM power supply that regulates

the VGLS output to 14.5-V. The VGLS supply is further regulated to 11-V on the GLx low-side gate driver

outputs. A smart gate-drive architecture provides the ability to dynamically adjust the output gate-drive current

strength allowing for the gate driver to control the power MOSFET VDS switching speed. This allows for the

removal of external gate drive resistors and diodes reducing BOM component count, cost, and PCB area. The

architecture also uses an internal state machine to protect against gate-drive short-circuit events, control the

half-bridge dead time, and protect against dV/dt parasitic turnon of the external power MOSFET.

The gate drivers can operate in either a single or dual supply architecture. In the single supply architecture, VM

can be tied to VDRAIN and is regulated to the correct supply voltages internally. In the dual supply architecture,

VM can be connected to a lower voltage supply from a more efficient switching regulator to improve the device

efficiency. VDRAIN stays connected to the external MOSFETs to set the correct charge pump and overcurrent

monitor reference.

The DRV8353 devices integrate three, bidirectional current-shunt amplifiers for monitoring the current level

through each of the external half-bridges using a low-side shunt resistor. The gain setting of the shunt amplifier

can be adjusted through the SPI or hardware interface with the SPI providing additional flexibility to adjust the

output bias point.

In addition to the high level of device integration, the DRV8353M family of devices provides a wide range of

integrated protection features. These features include power-supply undervoltage lockout (UVLO), gate drive

undervoltage lockout (GDUV), VDS overcurrent monitoring (OCP), gate-driver short-circuit detection (GDF), and

overtemperature shutdown (OTW/OTSD). Fault events are indicated by the nFAULT pin with detailed information

available in the SPI registers on the SPI device version.

The DRV8353M family of devices are available in 0.5-mm pin pitch, QFN surface-mount package. The QFN size

is 6 × 6 mm for the 40-pin package.

DRV8353M

SLVSFO2 – JULY 2020

www.ti.com

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