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ISO6741 Datenblatt(PDF) 26 Page - Texas Instruments

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Teilenummer ISO6741
Bauteilbeschribung  ISO674x General-Purpose Quad-Channel Digital Isolators with Robust EMC
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9 Layout
9.1 Layout Guidelines
A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 9-1). Layer stacking
should be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-
frequency signal layer.
• Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their
inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits
of the data link.
• Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
• Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100 pF/inch2.
• Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
If an additional supply voltage plane or signal layer is needed, add a second power or ground plane system to
the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also
the power and ground plane of each power system can be placed closer together, thus increasing the high-
frequency bypass capacitance significantly.
For detailed layout recommendations, refer to the Digital Isolator Design Guide.
9.1.1 PCB Material
For digital circuit boards operating below 150 Mbps, (or rise and fall times higher than 1 ns), and trace lengths of
up to 10 inches, use standard FR-4 UL94V-0 printed circuit boards. This PCB is preferred over cheaper
alternatives due to its lower dielectric losses at high frequencies, less moisture absorption, greater strength and
stiffness, and self-extinguishing flammability-characteristics.
9.2 Layout Example
10 mils
10 mils
40 mils
FR-4
0r ~ 4.5
Keep this
space free
from planes,
traces, pads,
and vias
Ground plane
Power plane
Low-speed traces
High-speed traces
Figure 9-1. Layout Example Schematic
ISO6741
SLLSFJ6 – AUGUST 2020
www.ti.com
26
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