LMK61E08 datasheet(24/54 Pages) TI

Teilenummer	LMK61E08

Bauteilbeschribung	LMK61E08 Ultra-Low Jitter Programmable Oscillator With Internal EEPROM

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Slave Address

S

Wr

A

CommandCode

A

Sr

Slave Address

Rd

A

...

P

A

Data Byte 0

A

Data Byte N-1

1

7

1

8

1

7

1

8

1

24

LMK61E08

SNAS805 – JUNE 2020

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Programming (continued)

5. Master writes the 7-bit Slave Address following by a Read bit.

6. Slave returns one or more data bytes as long as the Master continues to acknowledge them. The slave

increments the internal register address after each byte.

7. Master issues a Stop Condition to terminate the transaction.

Figure 32. Block Register Read Programming Sequence

8.5.4 Write SRAM

The on-chip SRAM is a volatile, shadow memory array used to temporarily store register data, and is intended

only for programming the non-volatile EEPROM. The SRAM has the identical data format as the EEPROM map.

The register configuration data can be transferred to the SRAM array through special memory access registers in

the register map. To successfully program the SRAM, the complete base array and at least one page should be

written. The following details the programming sequence to transfer the device registers into the SRAM.

1. Program the device registers to match a desired setting.

2. Write a 1 to R49[6]. This ensures that the device registers are copied to the SRAM.

The SRAM can also be written with particular values according to the following programming sequence.

1. Write the SRAM address in R51.

2. Write the desired data byte in R53 in the same I2C transaction and this data byte will be written to the

address specified in the step above. Any additional access that is part of the same transaction will cause the

SRAM address to be incremented and a write will take place to the next SRAM address. Access to SRAM

will terminate at the end of current I2C transaction.

NOTE

It is possible to increment SRAM address incorrectly when 2 successive accesses are

made to R51.

8.5.5 Write EEPROM

The on-chip EEPROM is a non-volatile memory array used to permanently store register data for a custom

device start-up configuration setting to initialize registers upon power up or POR. The EEPROM is comprised of

bits shown in the EEPROM Map. The transfer must first happen to the SRAM and then to the EEPROM. During

EEPROM write, R49[2] is a 1 and the EEPROM contents cannot be accessed. The following details the

programming sequence to transfer the entire contents of SRAM to EEPROM.

1. Make sure the Write SRAM procedure (Write SRAM) was done to commit the register settings to the SRAM

with start-up configurations intended for programming to the EEPROM.

2. Write 0xBE to R56. This provides basic protection from inadvertent programming of EEPROM.

3. Write a 1 to R49[0]. This programs the entire SRAM contents to EEPROM. Once completed, the contents in

R48 will increment by 1. R48 contains the total number of EEPROM programming cycles that are

successfully completed.

4. Write 0x00 to R56 to protect against inadvertent programming of EEPROM.

8.5.6 Read SRAM

The contents of the SRAM can be read out, one word at a time, starting with that of the requested address.

Following details the programming sequence for an SRAM read by address.

1. Write the SRAM address in R51.

2. The SRAM data located at the address specified in the step above can be obtained by reading R53 in the

same I2C transaction. Any additional access that is part of the same transaction will cause the SRAM

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