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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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TPS745-Q1 Datenblatt(PDF) 26 Page - Texas Instruments |
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TPS745-Q1 Datenblatt(HTML) 26 Page - Texas Instruments |
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26 / 45 page  26 TPS745-Q1 SBVS355A – JUNE 2019 – REVISED OCTOBER 2019 www.ti.com Product Folder Links: TPS745-Q1 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Application Information (continued) 8.1.7 Power-Good Function The power-good circuit monitors the voltage at the feedback pin to indicate the status of the output voltage. When the output voltage falls below the PG threshold voltage (PGLTH), the PG pin open-drain output engages and pulls the PG pin close to GND. When the output voltage exceeds PGHTH, the PG pin becomes high impedance. The open-drain output requires a pullup resistor. By connecting a pullup resistor to an external supply, any downstream device can receive power-good as a logic signal that can be used for sequencing. Additionally, the open-drain output can be tied to other open-drain outputs to implement AND logic. Make sure that the external pullup supply voltage results in a valid logic signal for the receiving device. Using a pullup resistor from 10 kΩ to 100 kΩ is recommended. The push-pull power-good option does not require the pullup resistor and instead has a high logic signal that correlates with the output voltage of the device. The push-pull option is supported only for VOUT ≥ 1.0 V. The push-pull option is supported only for VOUT ≥ 1.0 V. Do not tie the push-pull output to other logic outputs. When using a feed-forward capacitor (CFF), the time constant for the LDO start-up is increased whereas the power-good output time constant stays the same, possibly resulting in an invalid status of the power-good output. To avoid this issue, and to receive a valid PG output, make sure that the time constant of both the LDO start-up and the power-good output match, which can be done by adding a capacitor in parallel with the power-good pullup resistor. For more information, see the Pros and Cons of Using a Feedforward Capacitor with a Low- Dropout Regulator application report. The state of PG is only valid when the TPS745-Q1 operates above the minimum input voltage of the device and power-good is asserted, regardless of the output voltage state when the input voltage falls below the UVLO threshold minus the UVLO hysteresis. When the input voltage falls below approximately 0.8 V, there is not enough gate drive voltage to keep the open-drain, power-good device turned on and the power-good output pulled high. Connecting the power-good pullup resistor to the output voltage can help minimize this effect. 8.1.8 Feed-Forward Capacitor (CFF) For the adjustable-voltage version device, a feed-forward capacitor (CFF) can be connected from the OUT pin to the FB pin. CFF improves transient, noise, and PSRR performance, but is not required for regulator stability. Recommended CFF values are listed in the Recommended Operating Conditions table. A higher capacitance CFF can be used; however, the startup time increases. For a detailed description of CFF tradeoffs, see the Pros and Cons of Using a Feedforward Capacitor with a Low-Dropout Regulator application report. 8.1.9 Start-Up Sequencing If VEN is greater than VUVLO rising (min), the input pin (IN) must sink 1 mA of current to avoid the device being turned on with a floating input pin. |
Ähnliche Teilenummer - TPS745-Q1_V06 |
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Ähnliche Beschreibung - TPS745-Q1_V06 |
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