Datenblatt-Suchmaschine für elektronische Bauteile |
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TPS745-Q1 Datenblatt(PDF) 25 Page - Texas Instruments |
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TPS745-Q1 Datenblatt(HTML) 25 Page - Texas Instruments |
25 / 45 page 1-mm 2-mm A A Buried plane and bottom layer Cu ground planes are modeled with Area = A×A 25 TPS745-Q1 www.ti.com SBVS355A – JUNE 2019 – REVISED OCTOBER 2019 Product Folder Links: TPS745-Q1 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Application Information (continued) As shown in Figure 60, each layer has a copper plane of equal area. Figure 60. Board parameters used for simulation For a more comprehensive study of how thermal resistance varies with copper area and thickness, see the An empirical analysis of the impact of board layout on LDO thermal performance application report. As shown in Figure 61, modifying board layout to be more thermally enhanced can lower the RθJA value from 80.3°C/W to 46.8°C/W or better. Figure 61. TPS745-Q1 (WSON) RθJA versus Board Layout |
Ähnliche Teilenummer - TPS745-Q1_V06 |
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Ähnliche Beschreibung - TPS745-Q1_V06 |
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