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KM23V8105G Datenblatt(PDF) 1 Page - Samsung semiconductor

Teilenummer KM23V8105G
Bauteilbeschribung  8M-Bit (1Mx8 /512Kx16) CMOS MASK ROM
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Hersteller  SAMSUNG [Samsung semiconductor]
Direct Link  http://www.samsung.com/Products/Semiconductor
Logo SAMSUNG - Samsung semiconductor

KM23V8105G Datenblatt(HTML) 1 Page - Samsung semiconductor

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KM23V8105D(G)
CMOS MASK ROM
Pin Name
Pin Function
A0 - A1
Page Address Inputs
A2 - A18
Address Inputs
Q0 - Q14
Data Outputs
Q15 /A-1
Output 15(Word mode)/
LSB Address(Byte mode)
BHE
Word/Byte selection
CE
Chip Enable
OE
Output Enable
VCC
Power
VSS
Ground
N.C
No Connection
8M-Bit (1Mx8 /512Kx16) CMOS MASK ROM
The KM23V8105D(G) is a fully static mask programmable ROM
fabricated using silicon gate CMOS process technology, and is
organized either as 1,048,576 x 8 bit(byte mode) or as 524,288
x 16 bit(word mode) depending on BHE voltage level.(See
mode selection table)
This device includes PAGE read mode function, page read
mode allows 4 words(or 8 bytes) of data to read fast in the
same page, CE and A2 ~ A18 should not be changed.
This device operates with 3.0V or 3.3V power supply, and all
inputs and outputs are TTL compatible.
Because of its asynchronous operation, it requires no external
clock assuring extremely easy operation.
It is suitable for use in program memory of microprocessor, and
data memory, character generator.
The
KM23V8105D
is
packaged
in
a
42-DIP
and
the
KM23V8105DG in a 44-SOP.
GENERAL DESCRIPTION
FEATURES
• Switchable organization
1,048,576 x 8(byte mode)
524,288 x 16(word mode)
• Random access time/Page Access Time
3.3V Operation : 100/30ns(Max.)
3.0V Operation : 120/50ns(Max.)
• 4 Words / 8 bytes page access
• Supply voltage : single +3.0V/ single +3.3V
• Current consumption
Operating : 40mA(Max.)
Standby
: 30
µA(Max.)
• Fully static operation
• All inputs and outputs TTL compatible
• Three state outputs
• Package
-. KM23V8105D : 42-DIP-600
-. KM23V8105DG : 44-SOP-600
A18
X
A0~A1
AND
DECODER
BUFFERS
A2
Y
AND
DECODER
BUFFERS
MEMORY CELL
SENSE AMP.
CONTROL
LOGIC
MATRIX
(524,288x16/
1,048,576x8)
DATA OUT
BUFFERS
A-1
CE
OE
BHE
.
.
.
.
.
.
.
.
Q0/Q8
Q7/Q15
. . .
PIN CONFIGURATION
FUNCTIONAL BLOCK DIAGRAM
N.C
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE
VSS
OE
Q0
Q8
Q1
Q9
SOP
KM23V8105DG
1
2
44
43
3
4
42
41
5
6
40
39
7
8
38
37
9
10
36
35
11
12
34
33
13
14
32
31
15
16
30
29
17
18
28
27
19
20
26
25
21
22
24
23
Q2
Q10
Q3
Q11
Q11
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE
VSS
OE
Q0
Q8
Q1
Q9
DIP
KM23V8105D
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
Q2
Q10
Q3
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
Q4
Q12
Q5
Q13
Q6
VSS
Q14
Q7
Q15/A-1
A9
A10
A11
A12
A13
A14
A15
A16
BHE
VCC
N.C
A8
Q4
Q12
Q5
Q13
Q6
VSS
Q14
Q7
Q15/A-1
A9
A10
A11
A12
A13
A14
A15
A16
BHE
VCC
N.C
A8
N.C


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