Datenblatt-Suchmaschine für elektronische Bauteile |
|
74ABT3284VJG Datenblatt(PDF) 2 Page - National Semiconductor (TI) |
|
|
74ABT3284VJG Datenblatt(HTML) 2 Page - National Semiconductor (TI) |
2 / 12 page Functional Description The 74ABT3284 is a bi-directional registered data-path rout- ing device which can multiplexde-multiplex four 9-bit ‘‘A- side’’ data ports (Ports A B C D) ontofrom one 9-bit ‘‘X- side’’ port (Port X) Alternatively it can be configured for muxdemux of two 18-bit data paths (Ports A and C B and D) ontofrom one 18-bit data path (Ports X and Y) Each of the six 9-bit IO ports have independent active low TRI-STATE output enable control logic which can be con- figured to operate asynchronously or synchronously With MODE SO low direct asynchronous output control is pro- vided With MODE SO high output enable control is as- serted synchronously on the positive edge of the CP IN clock All IO port inputs are continuously active allowing output state feedback The four A-side ports (A B C D) contain independently enabled input and output data registers for storage of data passing in either direction The input register (AIR BIR CIR DIR) is loadedheld on the positive edge of CP AX when the respective Load Control pin (LDAI LDBI LDCI LDDI) is asserted highlow The Input Registers can be loaded with data from the corresponding A-side port The output register (AOR BOR COR DOR) is loadedheld on the positive edge of CP XA when the respective Load Control pin (LDAO LDBO LDCO LDDO) is asserted highlow The Output Registers can be loaded with data from Port X when MODE WS is asserted low When MODE WS is asserted high the Output Registers A and C can be loaded with Port X data and the B and D Output Registers can be loaded with data from Port Y When routing data from A-side to X-side Data Path Control is provided for the following options via the SA2X inputs Transparent mode where Input Register is bypassed but can simultaneously monitor A-side data Registered Mode where X-side receives data from the selected Input Regis- ters Readback Mode where X-side receives data from the selected Output Registers A-side data from Ports A B C or D can be selected to Port X via the XSEL data path select inputs Ports B or D can be selected to Port Y via the YSEL data path select input When routing data from X-side to A-side Data Path Control is provided for the following options via the ASEL inputs Transparent mode where Output Register is bypassed but can simultaneously monitor X-side data Registered Mode where the A-side Port receives data from the corresponding Output Register Readback Mode where the A-side Port re- ceives data from the corresponding Input Registers MODE WS asserted low selects Port X data to be passed to Ports A B C and D With MODE WS asserted high Port X data is passed to Ports A and C with Port Y data passed to Ports B and D All Data Path Control Inputs and InputOutput Register Load Enable Inputs are active high and can be asserted asynchronously or synchronously When MODE SC is low these inputs operate asynchronously When MODE SC is high the inputs are asserted synchronously on the positive edge of the CP IN clock When operating the Data Path Control andor the Output Enable Input groups with MODE SC andor MODE SO ‘‘hard wired’’ high for synchronous mode a single pre-clock of CP IN will be required following power-up to insure that all internal synchronous control registers are in the appropri- ate known state if the application requires ‘‘on the fly’’’ changes from asynchronous to synchronous operation then the respective controlenable pin data must be pre- clocked via CP IN and held steady prior to and during any low to high transition of the MODE SO or MODE SC to properly initiate the sync control registers for synchronous control mode Pin Descriptions Pin Name Description Operation OEa Output Enable Inputs SyncAsync (Active Low) LDaI Load Enable Inputs for the SyncAsync Input Registers LDaO Load Enable Inputs for the SyncAsync Output Registers ASEL(01) A-Side Data Path Select Inputs SyncAsync SA2X(01) X-Side Data Path Select Inputs SyncAsync XSEL(01) X-Port Data Path Select Inputs SyncAsync YSEL Y-Port Data Path Select Input SyncAsync MODE W Word Mode Select Input for SyncAsync the XY to A-Side Direction MODE SO Enable Input for Synchronous Async Output Enable Control MODE SC Enable Input for Synchronous Async Data Path Control CP IN Clock Input for Synchronous Control (Positive Edge Trigger) CP AX Clock Input for Input Registers (Positive Edge Trigger) CP XA Clock Input for Output Registers (Positive Edge Trigger) 2 |
Ähnliche Teilenummer - 74ABT3284VJG |
|
Ähnliche Beschreibung - 74ABT3284VJG |
|
|
Link URL |
Privatsphäre und Datenschutz |
ALLDATASHEETDE.COM |
War ALLDATASHEET hilfreich? [ DONATE ] |
Über Alldatasheet | Werbung | Kontakt | Privatsphäre und Datenschutz | Linktausch | Hersteller All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |