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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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CS4614-CM Datenblatt(PDF) 11 Page - Cirrus Logic |
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CS4614-CM Datenblatt(HTML) 11 Page - Cirrus Logic |
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11 / 24 page  DS292PP3 CIRRUS LOGIC PRELIMINARY PRODUCT BULLETIN JUNE 30, 5:03 PM 11 CS4614 CrystalClear™ SoundFusion™ PCI Audio Accelerator rameter RAM, and Sample RAM) into host memo- ry space. This allows the host to directly peek and poke RAM locations on the device. The relation- ship between the Base Address Registers in the CS4614 PCI Configuration Space and the host memory map is depicted in Figure 8. The bus mastering PCI bus interface complies with the PCI Local Bus Specification (version 2.1). PCI bus transactions As a target of a PCI bus transaction, the CS4614 supports the Memory Read (from internal registers or memory), Memory Write (to internal registers or memory), Configuration Read (from CS4614 configuration registers), Configuration Write (to CS4614 configuration registers), Memory Read Multiple (aliased to Memory Read), Memory Read Line (aliased to Memory Read), and the Memory Write and Invalidate (aliased to Memory Write) transfer cycles. The I/O Read, I/O Write, Interrupt Acknowledge, Special Cycles, and Dual Address Cycle transactions are not supported. As Bus Master, the CS4614 generates the Memory Read Multiple and Memory Write transactions. The Memory Read, Configuration Read, Configu- ration Write, Memory Read Line, Memory Write Host Memory North Bridge CPU South Bridge CS4297 PCI Bus PC/PCI (if used) Audio Out Audio In Figure 7. AC ‘97 Codec Interface CS4614 Accelerator 00h Device ID / Vendor ID Status / Command Class Code / Revision Base Address Register 0 Base Address Register 1 Misc. Control Direct I/O Registers (Memory Mapped, 4 kByte) Direct Memory Interface (Memory Mapped, 1 MByte) Device PCI Config. Space 04h 08h 0Ch 10h 14h Figure 8. Host Interface Base Address Registers |
Ähnliche Teilenummer - CS4614-CM |
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Ähnliche Beschreibung - CS4614-CM |
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