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TDA9965HL Datenblatt(PDF) 11 Page - NXP Semiconductors |
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TDA9965HL Datenblatt(HTML) 11 Page - NXP Semiconductors |
11 / 22 page 2004 Jul 05 11 Philips Semiconductors Product specification 12-bit, 5.0 V, 30 Msps analog-to-digital interface for CCD cameras TDA9965 Table 1 Serial interface programming Notes 1. PGA gain register must always be refreshed after clamp code register content has been changed. 2. When pin CLPADC = HIGH (SD1 = 1; serial interface), the ADC input is clamped to the voltage level of Vref. Pin Vref is connected to ground via a capacitor. When the power supplies increase from zero to VCC, the init-on-power block initializes the circuit as follows: • Cut-off frequency of the CTH circuit is set to: code fco(CTH) =0 • PGA gain control is set to: code GPGA =0 • Clamp code of the ADC is set to: code ADCCLP =0 • SHP and SHD sample on HIGH level; CLKADC activated with rising edge • CLPOB and CLPADC activated on HIGH level. Table 2 Standby selection Note 1. In case an external regulator is used, it has to be switched off in standby mode in order to avoid an extra power consumption of the TDA9965. ADDRESS BITS SDATA BITS SD0 to SD9 A1 A0 0 0 clamp reference of ADC (SD0 to SD9), note 1 0 1 cut-off frequency of CTH (SD0 to SD3) 1 0 PGA gain control (SD0 to SD9) 1 1 edge control for pulses SHP, SHD, CLPOB, CLPADC and CLKADC (note 2): SD0 = 1, SHP and SHD sample on LOW level SD1 = 1, CLPADC and CLPOB activated on HIGH level SD2 = 1, CLKADC activated with rising edge PIN STDBY DATA BITS SD9 to SD0 ICCA +ICCD HIGH logic 0 4 mA (typical); note 1 LOW active 84 mA (typical) |
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