ESS Technology, Inc.
SAM0487-031704
3
ES3890 PRODUCT BRIEF
ES3890 PIN DESCRIPTION
ES3890 PIN DESCRIPTION
Table 1 lists the pin descriptions for the ES3890.
Table 1
ES3890 Pin Description
Names
Pin Numbers
I/O
Definitions
VSSA
1, 9
G
Ground for analog circuits.
RSET
2
O
Reset. Internal current source generator. Connect this pin to a 510
Ω resistor to
ground.
VREF
3
O
Output reference voltage. Connect to a 0.01
−µF high-frequency bypass capacitor
to VSSA.
COMP
4
O
Compensation capacitance for low-pass filter on VDAC. Connect to a 0.01
−µF
high-frequency bypass capacitor to VSSA.
VCM
5
O
ADC analog voltage reference. Connect to a 0.01
−µF filter capacitor to VSSA.
MIC1, MIC2
6, 7
I
Microphone inputs.
VDDA
8
P
5.0V power supply for analog circuits.
AUX0[7:5]
10-12
I/O
General-purpose programmable I/O.
AUX3[2:0]
13-15
I/O
General-purpose programmable I/O.
LWR#
16
O
RISC interface Write Enable (active-low).
LOE#
17
O
RISC SRAM Output Enable (active-low).
CS0#
18
O
Chip select 0 for SRAM (active-low).
CS1#
19
O
Chip select 1 for SRAM (active-low).
CS3#
20
O
Chip select 3 for SRAM (active-low).
LD[7:0]
21-28
I/O
Data bus.
VCC
29, 42, 66, 95, 116
P
Core power supply (2.5V).
XIN
30
I
Crystal connection or input source of 27MHz.
XOUT
31
O
Crystal connection or output drive of an input clock source.
VSS
32, 41, 65, 97, 117
G
Ground for core.
LA[19:0]
33-40, 43-54
O
Address bus.
TDMFS
55
I
Frame signal from CDROM.
TDMDR
56
I
Data signal from CDROM.
TDMCLK
57
I
Clock signal from CDROM.
TBCK
58
O
Transmit clock when sending audio IIS data to external DAC.
SEL_PLL1
59
I
PLL mode select 1. Pulldown to ground to bypass PLL. Pullup to VCC for optimal
performance.
TWS
O
Audio strobe signal of IIS signals to external DAC.
SEL_PLL0
60
I
PLL mode select 0. Pulldown to GND to bypass PLL. Pullup to VCC for optimal
performance.
TSD
O
Audio data of IIS signals to external DAC.
MCLK
61
I/O
Media clock input to drive external audio devices or media clock output when
driven by external source into the ES3890.
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