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CX82100-51 Datenblatt(PDF) 10 Page - Synaptics Incorporated. |
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CX82100-51 Datenblatt(HTML) 10 Page - Synaptics Incorporated. |
10 / 226 page CX82100 Home Network Processor Data Sheet x Conexant Proprietary and Confidential Information 101306C Figures Figure 1-1. CX82100 HNP Major System Interface ..........................................................................................................1-3 Figure 1-2. CX82100 HNP Typical System Interface – Residential Gateway Firewall plus Router Application ...................1-4 Figure 1-3. CX82100 HNP Typical System Interface – Ethernet/HomePNA 2.0 Bridge Application ...................................1-4 Figure 1-4. CX82100 HNP Block Diagram........................................................................................................................1-5 Figure 1-5. Example of a Residential Gateway Firewall plus Router Application .............................................................1-11 Figure 1-6. Example of a HomePNA 2.0 Bridge Application............................................................................................1-12 Figure 2-1. CX82100-11/-12/-51/-52 HNP Hardware Interface Signals ............................................................................2-2 Figure 2-2. CX82100-11/-12/-51/-52 HNP Pin Signals-196-Pin FPBGA ...........................................................................2-3 Figure 2-3. CX82100-41/-42 HNP Hardware Interface Signals .........................................................................................2-5 Figure 2-4. CX82100-41/-42 HNP Pin Signals-196-Pin FPBGA ........................................................................................2-6 Figure 2-5. External Memory Interface Timing ...............................................................................................................2-21 Figure 2-6. Package Dimensions – 196-Pin 15 mm x 15 mm FPBGA.............................................................................2-23 Figure 3-1. HNP Memory Map .........................................................................................................................................3-2 Figure 3-2. Little-Endian Mode Addressing ......................................................................................................................3-4 Figure 3-3. Boot Procedure..............................................................................................................................................3-5 Figure 4-1. Address Generation in Direct Circular Buffer Mode ........................................................................................4-6 Figure 4-2. Embedded Tail Linked List Descriptor Example............................................................................................4-10 Figure 4-3. Indirect/Table Linked List Descriptor Example 1 ..........................................................................................4-12 Figure 4-4. Indirect/Table Linked List Descriptor Example 2 ..........................................................................................4-13 Figure 5-1. Host Master Mode Signals.............................................................................................................................5-1 Figure 5-2. Little-Endian Mode Data Bus Mapping ...........................................................................................................5-2 Figure 5-3. Waveforms for Host Master Mode Read Operation (CX82100-11/-12/-51/-52)..............................................5-6 Figure 5-4. Waveforms for Host Master Mode Write Operation (CX82100-11/-12/-51/-52) .............................................5-7 Figure 5-5. Waveforms for Host Master Mode Read Operation (CX82100-41/-42) ........................................................5-10 Figure 5-6. Waveforms for Host Master Mode Write Operation (CX82100-41/-42) ........................................................5-11 Figure 6-1. SDRAM Interface...........................................................................................................................................6-1 Figure 6-2. EMC Clocking Interface..................................................................................................................................6-6 Figure 6-3. EMC I/O Timing .............................................................................................................................................6-6 Figure 7-1. MAC Sublayer Partition, Relationship to OSI Reference Model ......................................................................7-1 Figure 7-2. Ethernet MAC Frame Format..........................................................................................................................7-2 Figure 7-3. EMAC Functional Block Diagram....................................................................................................................7-6 Figure 7-4. MII Connector................................................................................................................................................7-7 Figure 7-5. EMAC Transmit Frame Structure .................................................................................................................7-10 Figure 7-6. TMAC DMA Operation for Channel {x} = 1 or 3.............................................................................................7-14 Figure 7-7. A Perfect Address Filtering Setup Frame Buffer ...........................................................................................7-17 Figure 7-8. A Circuit for Dividing by G(x).......................................................................................................................7-18 Figure 7-9. Imperfect Address Filtering..........................................................................................................................7-20 Figure 7-10. Example of Imperfect Filtering Setup Frame...............................................................................................7-21 Figure 7-11. Sequence of Receiver DMA Operation .......................................................................................................7-26 Figure 8-1. Block Diagram of the USB Interface...............................................................................................................8-2 Figure 8-2. USB Transmit Data Flow ................................................................................................................................8-3 |
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