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CDC950DGG Datenblatt(PDF) 11 Page - Texas Instruments |
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CDC950DGG Datenblatt(HTML) 11 Page - Texas Instruments |
11 / 16 page CDC950 133MHz DIFFERENTIAL CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS/SERVERS SCAS646B − FEBRUARY 2001 − REVISED OCTOBER 2003 11 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PARAMETER MEASUREMENT INFORMATION tw VIH(REF) VT(REF) VIL(REF) 3 V 0 V Input CL (see Note A) Test Point From Output Under Test LOAD CIRCUIT for tr and tf VOLTAGE WAVEFORMS VT(REF) VT(REF) VT(REF) VT(REF) 3 V 0 V VDD 0 V Input tPLH VIH(REF) VT(REF) VIL(REF) tPHL VOH VOL tr tf tw(high) tw(low) Output tPZL tPZH tPLZ tPHZ VT(REF) VT(REF) VOL + 0.3 V VOH − 0.3 V ≈ 3 V VOL VOH ≈ 0 V Output Enable (High-Level Enabling) Output Waveform 1 S1 at 6 V (see Note B) Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS RL = 500 Ω RL = 500 Ω S1 VO(REF) OPEN GND CL (see Note A) From Output Under Test TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open VO(REF) GND S1 LOAD CIRCUIT For tpd and tsk NOTES: A. CL includes probe and jig capacitance. CL = 2 pF (HCLK, HCLK), CL = 20 pF (48 MHz, REF), CL = 30 pF (CLK33). B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 14.318 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. PARAMETER 3.3-V INTERFACE UNIT VIH(REF) High-level reference voltage 2.4 VIL(REF) Low-level reference voltage 0.4 V VT(REF) Input threshold reference voltage 1.5 V VO(REF) Off-state reference voltage 6 Figure 1. Load Circuit and Voltage Waveforms |
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