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BD9G500EFJ-LA Datenblatt(PDF) 16 Page - Rohm

Teilenummer BD9G500EFJ-LA
Bauteilbeschribung  7 V to 76 V Input, 5 A Integrated High ?밪ide MOSFET, Single Buck DC/DC Converter
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Hersteller  ROHM [Rohm]
Direct Link  http://www.rohm.com
Logo ROHM - Rohm

BD9G500EFJ-LA Datenblatt(HTML) 16 Page - Rohm

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TSZ02201-0F2F0AJ00280-1-2
© 2020 ROHM Co., Ltd. All rights reserved.
11.Jun.2020 Rev.001
www.rohm.com
TSZ22111 • 15 • 001
BD9G500EFJ-LA
VIN
0V
VOUT
Soft Start
hys
UVLO
OFF
Normal operation
Normal operation
UVLO
UVLO
ON
VOUT×0.95
VFB
IOUT
16/fOSC (Typ)
Reference Voltage
1.0 V(Typ)
100 ns(Typ)
400 ns(Typ)
OVDIS
(Over Volt age Discharge)
Discharge MOS
GATE
2.
Protective Functions - coutinued
2.2
Under Voltage Lockout Protection Function (UVLO)
This is under voltage lockout block. It shuts down the device when the VIN pin voltage falls to 6.4 V (Typ) or less.
The UVLO threshold voltage has a hysteresis of 200 mV (Typ).
2.3
Over Voltage Discharge Function (OVDIS)
When the FB pin voltage is 1.0 V (Typ) or more and 2.0 V (Typ) or less and remains in that state for 16 cycle, the
Discharge MOS On-time is set to 400 ns (Typ) and discharge output voltage.
Figure 35. OVDIS Timing Chart
2.4
Over Voltage Protection Function (OVP)
When the FB pin voltage is 1.2 V (Typ) or more, it turns High-Side MOSFET OFF. After FB pin voltage drops, it
returns to normal operation with hysteresis. This IC has Discharge MOS. This MOS turns on 100 ns (Typ) at each
duty cycle. When the FB pin voltage is 2.0 V (Typ) or more, it turns Discharge MOS off also.
2.5
Thermal Shutdown Function (TSD)
This is the thermal shutdown circuit that prevents heat damage to the IC. Normal operation should always be
within the IC’s power dissipation rating. However, if the rating is exceeded for a continued period and the junction
temperature (Tj) rises to 175 °C (Typ) or more, the TSD circuit will operate and turn OFF the output MOSFET.
When the Tj falls below the TSD threshold, the circuits are automatically restored to normal operation. Note that
the TSD circuit operates in a situation that exceeds the absolute maximum ratings and therefore, under no
circumstances, should the TSD circuit be used in a set design or for any purpose other than protecting the IC
from heat damage.
Figure 34. UVLO Timing Chart


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