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BD86852MUF-C Datenblatt(PDF) 10 Page - Rohm |
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BD86852MUF-C Datenblatt(HTML) 10 Page - Rohm |
10 / 46 page 10/43 TSZ02201-0A3A0AP00520-1-2 © 2020 ROHM Co., Ltd. All rights reserved. 03.Mar.2020 Rev.001 BD86852MUF-C www.rohm.com TSZ22111 • 15 • 001 Description of Blocks - continued CONTROL LOGIC Block (Protection of Timer-Latch) When the protection detection passes for 10 ms (Typ) or more, “Timer-Latch” works and all output turns off and PGOOD turns to low. The cancellation method of “Timer-Latch” is to activate either UVLO_VCC, UVLO_VREG or TSD, or to turn EN low. The following table shows the relation of protection (Timer-Latch). Table 3. Protection of Timer-Latch Protection PGOOD Notice ALL UVLO_VCC Low All output is off. Release Timer-Latch UVLO_VREG Low All output is off. Release Timer-Latch UVLO_VS Low When protection detect 8 times, Timer-Latch works. TSD Low All output is off. Release Timer-Latch DC/DC1 (VO1) OCPH Low(Note 1) High side FET is off. Timer-Latch after 10 ms. OCPN - Low side FET is off. VSOVP Low High and Low sides FET are off Timer-Latch after 10 ms. LVD Low Timer-Latch after 10 ms. OVD Low Timer-Latch after 10 ms. DC/DC2 (VO2) OCPH Low(Note 1) High side FET is off. Timer-Latch after 10 ms. OCPN - Low side FET is off. LVD Low Timer-Latch after 10 ms. OVD Low Timer-Latch after 10 ms. DC/DC3 (VO3) OCPH Low(Note 1) High side FET is off. Timer-Latch after 10 ms. OCPN - Low side FET is off. LVD Low Timer-Latch after 10 ms. OVD Low Timer-Latch after 10 ms. External LDO LVD Low Timer-Latch after 10 ms. OVD Low When more than 10 ms, Timer-Latch works. (Note 1) When protection detection is more than 10 ms, PGOOD turn into low. |
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