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DM9101
10/100Mbps Ethernet Physical Layer Single Chip Transceiver
Final
3
Version: DM9101-DS-F03
July 22, 1999
Features
•
10/100Base-TX physical-layer, single-chip transceiver
•
Compliant with IEEE 802.3u 100Base-TX standard
•
Compliant with ANSI X3T12 TP-PMD 1995 standard
•
Compliant with IEEE 802.3u Auto-negotiation protocol
for automatic link type selection
•
Supports the MII with serial management interface
•
Supports Full Duplex operation for 10 and 100Mbps
•
High performance 100Mbps clock generator and data
recovery circuitry
•
Adaptive equalization circuitry for 100Mbps receiver
•
Controlled output edge rates in 100Mbps
•
Supports a 10Base-T interface without the need for
an external filter
•
Provides Loop-back mode for system diagnostics
•
Includes Flexible LED configuration capability
•
Digital clock recovery circuit using advanced digital
algorithm to reduce jitter
•
Low-power, high-performance CMOS process
•
Available in both a 100 pin LQFP and a 100 QFP
package
Pin Configuration: DM9101E LQFP
DM9101E
75
74
73
72
71
70
69
68
67
66
65
64
63
62
6
1
60
59
58
57
56
55
54
53
52
5
1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
1
2
3
4
5
6
7
8
9
TX_ER/TXD4
COL
CRS
RX_CLK
DVCC
DGND
RXD0
RXD1
RXD2
RXD3
DVCC
DGND
MDIO
MDC
TX_CLK
TX_EN
DVCC
DGND
TXD0
TXD1
TXD2
TXD3
TXLED#
RXLED#
LINKLED#
NC
NC
NC
AGND
AVCC
AVCC
RXI-
RXI+
AGND
AGND
10TXO-
10TXO+
AVCC
AVCC
AGND
AGND
NC
NC
AVCC
AVCC
AGND
AGND
100TXO-
100TXO+
AVCC