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ST7565S
Ver 0.3c
2/73
2002/07/22
S
ST
T7
75
56
65
5S
S P
Pa
ad
d A
Arrrra
an
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em
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Chip Size:
9,336μm x 1,000 μm
Bump Pitch:
58μm(Min.)
Bump Size:
PAD No. 001〜012
40μm x 90μm
PAD No. 013〜102
56μm x 60μm
PAD No. 103〜114
40μm x 90μm
PAD No. 115
102μm x 37.5μm
PAD No. 116〜128
90μm x 40μm
PAD No. 129〜276
40μm x 90μm
PAD No. 277〜289
90μm x 40μm
PAD No. 290
102μm x 37.5μm
Bump Height:
18μm(Typ)
Chip Thickness: 660μm
VOUT maximum -13V (+10% Range)
ST7565S Temperature gradient = -0.05%/°C
Logic power supply VDD – VSS = 1.8V to 3.3 V (+10% Range)
Add new booster ratio 5 times and 6 times
Use select pin to define display duty as following table
SEL 3 , 2 , 1
DUTY
BIAS
0 , 0 , 0
1/65
1/9 or 1/7
0 , 0 , 1
1/49
1/8 or 1/6
0 , 1 , 0
1/33
1/6 or 1/5
0 , 1 , 1
1/55
1/8 or 1/6
1 , 0 , 0
1/53
1/8 or 1/6
1, X , X
-----
-----
128
(-4558,-410)
277
(4558,-410)
22um 30um 22um
30um
39um
38um 30um
38um
30um
115
1
114
(3528,395)
12
13
．．．．．．．．
．
．
．
．
．
．
．．．．．．．
．
．
．
．
．
．
．
．
129
276
290
．．．．
X
Y
(0,0)
ST7565S
PAD DIAGRAM
38
um
24um
15
um
15
um
15
um 15um
30
um
38
um
15
um
15
um
15
um
15
um
15 um
15 um
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