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UPSD3354DV-40T6 Datenblatt(PDF) 7 Page - STMicroelectronics |
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UPSD3354DV-40T6 Datenblatt(HTML) 7 Page - STMicroelectronics |
7 / 231 page 7/231 uPSD33xx SUMMARY DESCRIPTION The Turbo uPSD33xx Series combines a powerful 8051-based microcontroller with a flexible memory structure, programmable logic, and a rich periph- eral mix to form an ideal embedded controller. At its core is a fast 4-cycle 8032 MCU with a 6-byte instruction prefetch queue (PFQ) and a 4-entry ful- ly associative branching cache (BC) to maximize MCU performance, enabling loops of code in smaller localities to execute extremely fast. Code development is easily managed without a hardware In-Circuit Emulator by using the serial JTAG debug interface. JTAG is also used for In- System Programming (ISP) in as little as 10 sec- onds, perfect for manufacturing and lab develop- ment. The 8032 core is coupled to Programmable System Device (PSD) architecture to optimize the 8032 memory structure, offering two independent banks of Flash memory that can be placed at vir- tually any address within 8032 program or data ad- dress space, and easily paged beyond 64K bytes using on-chip programmable decode logic. Dual Flash memory banks provide a robust solution for remote product updates in the field through In-Ap- plication Programming (IAP). Dual Flash banks also support EEPROM emulation, eliminating the need for external EEPROM chips. General pur- pose programmable logic (PLD) is included to build an endless variety of glue-logic, saving exter- nal logic devices. The PLD is configured using the software development tool, PSDsoft Express, available from the web at www.st.com/psm, at no charge. The uPSD33xx also includes supervisor functions such as a programmable watchdog timer and low-voltage reset. Figure 2. Block Diagram PA0:7 PB0:7 PD1:2 PC0:7 MCU Bus P4.0:7 P1.0:7 P3.0:7 uPSD33xx Dedicated Pins Supervisor: Watchdog and Low-Voltage Reset 1st Flash Memory: 64K, 128K, or 256K Bytes 2nd Flash Memory: 16K or 32K Bytes SRAM: 2K, 8K, or 32K Bytes Programmable Decode and Page Logic General Purpose Programmable Logic, 16 Macrocells (8) GPIO, Port A (80-pin only) (8) GPIO, Port B (4) GPIO, Port C (2) GPIO, Port D JTAG ICE and ISP 8032 Address/Data/Control Bus (80-pin device only) V CC, VDD, GND, Reset, Crystal In Turbo 8032 Core PFQ & BC (3) 16-bit Timer/ Counters (2) External Interrupts I 2C SPI (8) 10-bit ADC UART0 (8) GPIO, Port 1 (8) GPIO, Port 3 (8) GPIO, Port 4 UART1 Optional IrDA Encoder/Decoder 16-bit PCA (6) PWM, CAPCOM, TIMER AI08875 |
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Ähnliche Beschreibung - UPSD3354DV-40T6 |
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