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ES35P40-75CG2Y Datenblatt(PDF) 9 Page - Excel Semiconductor Inc. |
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ES35P40-75CG2Y Datenblatt(HTML) 9 Page - Excel Semiconductor Inc. |
9 / 35 page ES I ES I 9 Rev. 0D May 11 , 2006 ES25P40 Excel Semiconductor inc. ADVANCED INFORMATION INSTRUCTIONS All instructions, addresses, and data are shifted in and out of the device, starting with the most signifi- cant bit. Serial Data Input (SI) is sampled on the first rising edge of Serial Clock (SCK) after Chip Select (CS#) is driven Low. Then, the one byte instruction code must be shifted in to the device, most signifi- cant bit first, on Serial Data Input (SI), each bit being latched on the rising edges of Serial Clock (SCK). The instruction set is listed in Table 3. Every instruction sequence starts with a one byte instruction code. Depending on the instruction, this might be followed by address bytes, or by data bytes, or by both or none. Chip Select (CS#) must be driven High after the last bit of the instruction sequence has been shifted in. In the case of a Read Data Bytes (READ), Read Sta- tus Register (RDSR), Read Data Bytes at higher speed (FAST_READ), Read Identification (RDID) , Read Manufacturer and Device ID (RDMD), Read Parameter Page (RDPARA) and Fast Read Parame- ter Page (FRDPARA) instructions, the shifted-in instruction sequence is followed by a data-out sequence. Chip Select (CS#) can be driven High after any bit of the data-out sequence is being shifted out to ter- minate the transaction. In the case of a Page Program (PP), Program Parameter Page (PPP), Sector Erase (SE), Bulk Erase (BE), Parameter Page Erase(PE), Write Sta- tus Register (WRSR), Write Enable (WREN), Deep Power Down (DP) or Write Disable (WRDI) instruc- tion, Chip Select (CS#) must be driven High exactly at a byte boundary, otherwise the instruction is rejected, and is not executed. That is, Chip Select (CS#) must driven High when the number of clock pulses after Chip Select (CS#) being driven Low is an exact multiple of eight. All attempts to access the memory array during a Write Status Register cycle, Program cycle or Erase cycle are ignored, and the internal Write Status Register cycle, Program cycle or Erase cycle con- tinues unaffected. |
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