Datenblatt-Suchmaschine für elektronische Bauteile |
|
GS81032AT-4I Datenblatt(PDF) 1 Page - GSI Technology |
|
GS81032AT-4I Datenblatt(HTML) 1 Page - GSI Technology |
1 / 23 page Rev: 1.01 7/2001 1/23 © 2000, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS81032AT/Q-150/138/133/117/100/66 32K x 32 1M Synchronous Burst SRAM 150 MHz–66 MHz 9 ns–18 ns 3.3 V VDD 3.3 V and 2.5 V I/O TQFP, QFP Commercial Temp Industrial Temp Features • FT pin for user-configurable flow through or pipeline operation • Single Cycle Deselect (SCD) operation • 3.3 V +10%/–5% core power supply • 2.5 V or 3.3 V I/O supply • LBO pin for Linear or Interleaved Burst mode • Internal input resistors on mode pins allow floating mode pins • Default to Interleaved Pipeline mode • Byte Write (BW) and/or Global Write (GW) operation • Common data inputs and data outputs • Clock Control, registered, address, data, and control • Internal self-timed write cycle • Automatic power-down for portable applications • JEDEC-standard 100-lead TQFP or QFP package Functional Description Applications The GS81032A is a 1,048,576-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support. Controls Addresses, data I/Os, chip enables (E1, E2, E3), address burst control inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edge-triggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter may be configured to count in either linear or interleave order with the Linear Burst Order (LBO) input. The burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance. Flow Through/Pipeline Reads The function of the Data Output register can be controlled by the user via the FT mode pin (Pin 14). Holding the FT mode pin low places the RAM in Flow Through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM in Pipeline mode, activating the rising- edge-triggered Data Output Register. SCD Pipelined Reads The GS81032A is an SCD (Single Cycle Deselect) pipelined synchronous SRAM. DCD (Dual Cycle Deselect) versions are also available. SCD SRAMs pipeline deselect commands one stage less than read commands. SCD RAMs begin turning off their outputs immediately after the deselect command has been captured in the input registers. Byte Write and Global Write Byte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the byte write control inputs. Sleep Mode Low power (Sleep mode) is attained through the assertion (high) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode. Core and Interface Voltages The GS81032A operates on a 3.3 V power supply and all inputs/outputs are 3.3 V- and 2.5 V-compatible. Separate output power (VDDQ) pins are used to decouple output noise from the internal circuit. -150 -138 -133 -117 -100 -66 Unit Pipeline 3-1-1-1 tCycle tKQ IDD 6.6 3.8 270 7.25 4 245 7.5 4 240 8.5 4.5 210 10 5 180 12.5 6 150 ns ns mA Flow Through 2-1-1-1 tCycle tKQ IDD 10.5 9 170 15 9.7 120 15 10 120 15 11 120 15 12 120 20 18 95 ns ns mA |
Ähnliche Teilenummer - GS81032AT-4I |
|
Ähnliche Beschreibung - GS81032AT-4I |
|
|
Link URL |
Privatsphäre und Datenschutz |
ALLDATASHEETDE.COM |
War ALLDATASHEET hilfreich? [ DONATE ] |
Über Alldatasheet | Werbung | Kontakt | Privatsphäre und Datenschutz | Linktausch | Hersteller All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |