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GS84032T-166 Datenblatt(PDF) 1 Page - GSI Technology |
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GS84032T-166 Datenblatt(HTML) 1 Page - GSI Technology |
1 / 31 page Rev: 2.05 6/2000 1/31 © 1999, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS84018/32/36T/B-180/166/150/100 256K x 18, 128K x 32, 128K x 36 4Mb Sync Burst SRAMs 180Mhz - 100Mhz 3.3V VDD 3.3V & 2.5V I/O TQFP, BGA Commercial Temp Industrial Temp Features • FT pin for user configurable flow through or pipelined operation. • Single Cycle Deselect (SCD) Operation. • 3.3V +10%/-5% Core power supply • 2.5V or 3.3V I/O supply. • LBO pin for linear or interleaved burst mode. • Internal input resistors on mode pins allow floating mode pins. • Default to Interleaved Pipelined Mode. • Byte write (BW) and/or global write (GW) operation. • Common data inputs and data outputs. • Clock Control, registered, address, data, and control. • Internal Self-Timed Write cycle. • Automatic power-down for portable applications. • JEDEC standard 100-lead TQFP or 119 Bump BGA package. Functional Description Applications The GS84018/32/36 is a 4,718,592 bit (4,194,304 bit for x32 version) high performance synchronous SRAM with a 2 bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPU’s, the device now finds application in synchronous SRAM applications ranging from DSP main store to networking chip set support. The GS84018/32/36 is available in a JEDEC standard 100-lead TQFP or 119 Bump BGA package. Controls Addresses, data I/O’s, chip enables (E1, E2, E3), address burst control inputs (ADSP, ADSC, ADV) and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive edge triggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter may be configured to count in either linear or interleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance. Flow Through / Pipeline Reads The function of the Data Output register can be controlled by the user via the FT mode pin/bump (pin 14 in the TQFP and bump 5R in the BGA, ) . Holding the FT mode pin/bump low places the RAM in Flow through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM in Pipelined Mode, activating the rising edge triggered Data Output Register. SCD Pipelined Reads The GS84018/32/36 is an SCD (Single Cycle Deselect) pipelined synchronous SRAM. DCD (Dual Cycle Deselect) versions are also available.SCD SRAMs pipeline deselect commands one stage less than read commands. SCD RAMs begin turning off their outputs immediately after the deselect command has been captured in the input registers. Byte Write and Global Write Byte write operation is performed by using byte write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs. Sleep Mode Low power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode. Core and Interface Voltages The GS84018/32/36 operates on a 3.3V power supply and all inputs/ outputs are 3.3V and 2.5V compatible. Separate output power (VDDQ) pins are used to de-couple output noise from the internal circuit. -180 -166 -150 -100 Pipeline 3-1-1-1 tCycle tKQ IDD 5.5ns 3.2ns 330mA 6.0ns 3.5ns 310mA 6.6ns 3.8ns 275mA 10ns 4.5ns 190mA Flow Through 2-1-1-1 tKQ tCycle IDD 8ns 10ns 190mA 8.5ns 10ns 190mA 10ns 10ns 190mA 12ns 15ns 140mA |
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Ähnliche Beschreibung - GS84032T-166 |
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