21:3 LVDS Receiver
CS5821
BLOCK DIAGRAM
GENERAL DESCRIPTION
Century Semiconductor Inc.
FEATURES
USA:
1485 Saratoga Ave. #200
San Jose, CA, 95129
Tel: 408-973-8388 Fax: 408-973-9388
Sales@century-semi.com
Sales@century-semi.com.tw
www.century-semi.com
Rev.0.5 May 2001
page 1 of 14
Century Semiconductor, Inc.
Taiwan:
No. 2, Industry East Rd. 3rd,
Science-Based Industrial Park, Hsin-Chu, Taiwan
Tel: 886-3-5784866 Fax: 886-3-5784349
CS5821 receives three LVDS data channels and
one LVDS clock channel.
Each data channel is
deserialized into 7-bit parallel data bus for output.
The clock channel is used for frame sync and fed into
an internal PLL that generates the 7X serial clock
used in the deserializer. A digital phase alignment
circuit can generate the sampling clock of the
deserializer front-end. The frame sync clock aligned
to the output 7-bit data is also output for timing
reference.
CS5821 supports open-safe design of LVDS when
the input is not connected to LVDS drivers and the
receiver outputs are forced low. Putting CS5821 into
inhibit mode by a shutdown control (SHTDNN) signal
can lower power consumption.
• Three 7-bit serial data LVDS channels and one
clock LVDS channel.
• Compatible with ANSI TIA/EIA-644 LVDS stan-
dard.
• Wide serial clocking speed ranges from 31MHz to
68MHz.
• Support open-safe LVDS design.
• Fully integrated on-chip PLL and digital phase
alignment provide accurate deserializer operation.
• Support power-down mode.
• 5V/3.3V tolerant data input.
• Single 3.3V supply operation.
• CMOS low power consumption.
• Functional compatible with DS90CF364 and
SN75LVDS86.
• Available in 48-pin TSSOP package.
SERIAL-IN PARALLEL-OUT
D0-D6
7-Bit SHIFT REGISTER
CLK
DIN
SERIAL-IN PARALLEL-OUT
7-Bit SHIFT REGISTER
DIN
SERIAL-IN PARALLEL-OUT
7-Bit SHIFT REGISTER
DIN
CLK
CLK
PHASE LOCK LOOP
7xCLK
CONTROL LOGIC
D7-D13
D14-D20
SHTDNN
AIP
AIM
BIP
BIM
CIP
CIM
CKIP
CKIM
CS5821
AND
PHASE ALIGNER
CLKOUT
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