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74ALVCH16646 Datenblatt(PDF) 2 Page - NXP Semiconductors |
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74ALVCH16646 Datenblatt(HTML) 2 Page - NXP Semiconductors |
2 / 12 page Philips Semiconductors Product specification 74ALVCH16646 16-bit bus transceiver/register (3-State) 2 1998 Sep 03 853-2116 19959 FEATURES • Complies with JEDEC standard no. 8-1A • CMOS low power consumption • MULTIBYTETM flow-through pin-out architecture • Low inductance, multiple V CC and ground pins for minimum noise and ground bounce • Direct interface with TTL levels • Current drive ± 24 mA at 3.0 V • Output drive capability 50Ω transmission lines @ 85°C • All inputs have bushold circuitry DESCRIPTION The 74ALVCH16646 consists of 16 non-inverting bus transceiver circuits with 3-State outputs, D-type flip-flops and control circuitry arranged for multiplexed transmission of data directly from the internal registers. Data on the ‘A’ or ‘B’ bus will be clocked in the internal registers, as the appropriate clock (CPAB or CPBA) goes to a HIGH logic level. Output enable (OE) and direction (DIR) inputs are provided to control the transceiver function. In the transceiver mode, data present at the high-impedance port may be stored in either the ‘A’ or ‘B’ register, or in both. The select source inputs (SAB and SBA) can multiplex stored and real-time (transparent mode) data. The direction (DIR) input determines which bus will receive data when OE is active (LOW). In the isolation mode (OE = HIGH), ‘A’ data may be stored in the ‘B’ register and/or ‘B’ data may be stored in the ‘A’ register. When an output function is disabled, the input function is still enabled and may be used to store and transmit data. Only one of the two buses, ‘A’ or ‘B’ may be driven at a time. To ensure the high impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. PIN CONFIGURATION 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 1DIR 1CPAB 1SAB GND 1A0 1A1 VCC 1A3 1A4 GND 1A5 1A6 1A7 2A0 1A2 2A1 2A2 GND 2A3 2A4 2B4 2B3 GND 2B2 2B1 2B0 1B7 1B6 1B5 GND 1B4 1B3 1B2 VCC 1B1 1B0 GND 1SBA 1CPBA 1OE 21 22 23 24 33 34 35 36 2A5 VCC 2A6 2A7 2B7 2B6 VCC 2B5 25 26 27 28 29 30 31 32 GND 2SAB 2CPAB 2DIR 2OE 2CPBA 2SBA GND SY00011 QUICK REFERENCE DATA GND = 0V; Tamb = 25°C; tr = tf ≤ 2.5ns SYMBOL PARAMETER CONDITIONS TYPICAL UNIT tPHL/tPLH Propagation delay nAx to nBx VCC = 2.5V, CL = 30pF VCC = 3.3V, CL = 50pF 2.6 2.7 ns CI Input capacitance 3.0 pF C Power dissipation capacitance per channel V = GND to VCC1 Outputs enabled 36 pF CPD Power dissipation capacitance per channel VI = GND to VCC1 Outputs disabled 4 pF Fmax Maximum clock frequency VCC = 2.5V, CL = 30pF VCC = 3.3V, CL = 50pF 300 320 MHz NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + S (CL × VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacity in pF; fo = output frequency in MHz; VCC = supply voltage in V; S (CL × VCC2 × fo) = sum of outputs. ORDERING INFORMATION PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER 56-Pin Plastic TSSOP Type II –40 °C to +85°C 74ALVCH16646 DGG ACH16646 DGG SOT364-1 |
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