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74AVC16835DGG Datenblatt(PDF) 3 Page - NXP Semiconductors |
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74AVC16835DGG Datenblatt(HTML) 3 Page - NXP Semiconductors |
3 / 10 page Philips Semiconductors Preliminary specification 74AVC16835 18-bit Registered Driver (3-State) 1999 Jul 23 3 PIN DESCRIPTION PIN NUMBER SYMBOL NAME AND FUNCTION 1, 2, 55 NC No connection 3, 5, 6, 8, 9, 10, 12, 13, 14, 15, 16, 17, 19, 20, 21, 23, 24, 26 Y0 to Y17 Data outputs 4, 11, 18, 25, 32, 39, 46, 53, 56 GND Ground (0V) 7, 22, 35, 50 VCC Positive supply voltage 27 OE Output enable input (active LOW) 28 LE Latch enable input (active HIGH) 30 CP Clock input 54, 52, 51, 49, 48, 47, 45, 44, 43, 42, 41, 40, 38, 37, 36, 34, 33, 31 A0 to A17 Data inputs LOGIC SYMBOL SH00138 CP LE D OE CP LE A0 Y0 TO THE 17 OTHER CHANNELS LOGIC SYMBOL (IEEE/IEC) 1 ∇ 1 30 28 54 52 51 49 48 47 45 44 43 42 41 40 38 37 36 34 33 31 3 5 6 8 9 10 12 13 14 15 16 17 19 20 21 23 24 26 3D 27 2C3 EN1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 OE CP Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 LE C3 G2 SH00154 FUNCTION TABLE INPUTS OUTPUTS OE LE CP A OUTPUTS H X X X Z L H X L L L H X H H L L ↑ L L L L ↑ H H L L H X Y01 L L L X Y02 H = HIGH voltage level L = LOW voltage level X = Don’t care Z = High impedance “off” state ↑ = LOW-to-HIGH level transition NOTES: 1. Output level before the indicated steady-state input conditions were established, provided that CP is high before LE goes low. 2. Output level before the indicated steady-state input conditions were established. |
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