Philips Semiconductors

Product specification

74F169

4-bit up/down binary synchronous counter

1996 Jan 05

9

TIMING DIAGRAM (Typical Load, Count, and Inhibit Sequences)

78

9

0

1

2

2

1

0

9

8

7

COUNT UP

COUNT DOWN

INHIBIT

LOAD

PE

TC

CEP and CET

U/D

D0

D1

D2

D3

Q0

Q1

Q2

Q3

CP

2

SEQUENCE

SF00797

NOTES:

The operation of the 74F169 is similar to the Illustration above.

1. Load (preset) to BCD seven

2. Count up to eight, nine (maximum), zero, one, and two

3. Inhibit

4. Count down to one, zero (minimum), nine, eight, and seven

TEST CIRCUIT AND WAVEFORM

tw

90%

VM

10%

90%

VM

10%

90%

VM

10%

90%

VM

10%

NEGATIVE

PULSE

POSITIVE

PULSE

tw

AMP (V)

0V

0V

tTHL (tf )

INPUT PULSE REQUIREMENTS

rep. rate

1MHz

500ns

2.5ns

2.5ns

Input Pulse Definition

VCC

family

74F

D.U.T.

PULSE

GENERATOR

RL

CL

RT

VIN

VOUT

Test Circuit for Totem-Pole Outputs

DEFINITIONS:

see AC ELECTRICAL CHARACTERISTICS for value.

see AC ELECTRICAL CHARACTERISTICS for value.

pulse generators.

tTHL (tf )

tTLH (tr )

tTLH (tr )

AMP (V)

amplitude

3.0V

1.5V

SF00006