MOTOROLA CMOS LOGIC DATA

3

MC14521B

Characteristic

Symbol

VDD

Vdc

Min

Typ #

Max

Unit

Output Rise and Fall Time (Counter Outputs)

tTLH, tTHL = (1.5 ns/pF) CL + 25 ns

tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns

tTLH, tTHL = (0.55 ns/pF) CL + 12.5 ns

tTLH, tTHL

5.0

10

15

—

—

—

100

50

40

200

100

80

ns

Propagation Delay Time

Clock to Q18

tPHL, tPLH = (1.7 ns/pF) CL + 4415 ns

tPHL, tPLH = (0.66 ns/pF) CL + 1667 ns

tPHL, tPLH = (0.5 ns/pF) CL + 1275 ns

tPHL, tPLH

5.0

10

15

—

—

—

4.5

1.7

1.3

9.0

3.5

2.7

µs

Clock to Q24

tPHL, tPLH = (1.7 ns/pF) CL + 5915 ns

tPHL, tPLH = (0.66 ns/pF) CL + 2167 ns

tPHL, tPLH = (0.5 ns/pF) CL + 1675 ns

5.0

10

15

—

—

—

6.0

2.2

1.7

12

4.5

3.5

Propagation Delay Time

Reset to Qn

tPHL = (1.7 ns/pF) CL + 1215 ns

tPHL = (0.66 ns/pF) CL + 467 ns

tPHL = (0.5 ns/pF) CL + 350 ns

tPHL

5.0

10

15

—

—

—

1300

500

375

2600

1000

750

ns

Clock Pulse Width

tWH(cl)

5.0

10

15

385

150

120

140

55

40

—

—

—

ns

Clock Pulse Frequency

fcl

5.0

10

15

—

—

—

3.5

9.0

12

2.0

5.0

6.5

MHz

Clock Rise and Fall Time

tTLH, tTHL

5.0

10

15

—

—

—

—

—

—

15

5.0

4.0

µs

Reset Pulse Width

tWH(R)

5.0

10

15

1400

600

450

700

300

225

—

—

—

ns

Reset Removal Time

trem

5.0

10

15

30

0

– 40

– 200

– 160

– 110

—

—

—

ns

* The formulas given are for the typical characteristics only at 25

_C.

#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

Figure 1. Power Dissipation Test Circuit and Waveform

PULSE

GENERATOR

VDD

VDD

VDD

VSS

VSS

Q18

Q19

Q20

Q21

Q22

Q23

Q24

CL

CL

CL

CL

CL

CL

CL

ID

IN 2

R

500

µF

0.01

µF

CERAMIC

20 ns

20 ns

VDD

0 V

Vin

50% DUTY CYCLE

90%

10%

50%