December 1990

2

Philips Semiconductors

Product specification

7-stage binary ripple counter

74HC/HCT4024

FEATURES

• Output capability: standard

GENERAL DESCRIPTION

The 74HC/HCT4024 are high-speed Si-gate CMOS

devices and are pin compatible with the “4024” of the

“4000B” series. They are specified in compliance with

JEDEC standard no. 7A.

The 74HC/HCT4024 are 7-stage binary ripple counters

with a clock input (CP), an overriding asynchronous

master reset input (MR) and seven fully buffered parallel

The counter advances on the HIGH-to-LOW transition of

CP.

A HIGH on MR clears all counter stages and forces all

outputs LOW, independent of the state of CP.

Each counter stage is a static toggle flip-flop.

Schmitt-trigger action in the clock input makes the circuit

highly tolerant to slower clock rise and fall times.

APPLICATIONS

• Frequency dividing circuits

• Time delay circuits

QUICK REFERENCE DATA

Notes

ORDERING INFORMATION

See

SYMBOL

PARAMETER

CONDITIONS

TYPICAL

UNIT

HC

HCT

14

14

ns

maximum clock frequency

90

70

MHz

input capacitance

3.5

3.5

pF

power dissipation capacitance per package

notes 1 and 2

25

27

pF