74HCT7731 datasheet(2/8 Pages) PHILIPS

Teilenummer	74HCT7731

Bauteilbeschribung	Quad 64-bit static shift register

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Hersteller	PHILIPS [NXP Semiconductors]

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September 1993

2

Philips Semiconductors

Product speciﬁcation

Quad 64-bit static shift register

74HC/HCT7731

FEATURES

• Frequency range DC to 100 MHz.

• Separate serial data inputs

• Cascadable

• Functionally compatible with

HEF 4731

• Includes recycling mode

• Direct shift out

• Output capability: Standard

• ICC category: LSI.

APPLICATIONS

• Data storage

• Delay line.

GENERAL DESCRIPTION

The HC/HCT7731 are high-speed

Si-gate CMOS devices. They are

specified in compliance with JEDEC

standard no. 7A.

The HC/HCT7731 are quad 64-bit

static shift registers with a recycling

mode. Each register has separate

data inputs Da to Dd, clock inputs CPa

to CPd and data outputs Qa to Qd.

Data shifts one place towards the

output, each LOW to HIGH transition

of the clock pulse. Each recycling

mode input controls two registers

RECab for registers A and B and

RECcd for registers C and D. When

the REC input is HIGH, the device is

in the recycling mode and data at the

output is shifted back into the input of

the register, so after 64 clock pulses

the contents of a register is again in

its original position. This enables the

user to tap off data from any position.

When the REC input is LOW external

data can be shifted in.

QUICK REFERENCE DATA

GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns.

Notes

1. CPD is used to determine the dynamic power dissipation (PD in µW):

PD = (CPD x VCC2 x fi) + (CL + VCC2 x fo) + (Ipull-up x VCC)

where:

fi = input frequency in MHz.

fo = output frequency in MHz.

VCC = supply voltage in V.

CL = output load capacitance in pF.

Ipull-up = pull-up currents in µA.

2. For HC the condition is VI = GND to VCC

For HCT the condition is VI = GND to VCC − 1.5 V.

3. See also power dissipation information.

ORDERING INFORMATION

SYMBOL

PARAMETER

CONDITIONS

TYP.

UNIT

HC

HCT

tPHL/tPLH

propagation delay

CPa-d to Qa-d

CL = 15 pF;

VCC = 5 V

15

20

ns

fmax

maximum clock

frequency

100

MHz

CI

input capacitance

3.5

pF

CPD

power dissipation

capacitance per register

notes 1, 2

and 3

58

61

pF

EXTENDED TYPE

NUMBER

PACKAGE

PINS

PIN POSITION

MATERIAL

CODE

74HC/HCT7731N

16

DIL

plastic

SOT38Z

74HC/HCT7731D

16

SO16

plastic

SOT109A

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