Datenblatt-Suchmaschine für elektronische Bauteile |
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74LV595PWDH Datenblatt(PDF) 8 Page - NXP Semiconductors |
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74LV595PWDH Datenblatt(HTML) 8 Page - NXP Semiconductors |
8 / 16 page Philips Semiconductors Product specification 74LV595 8-bit serial-in/serial or parallel-out shift register with output latches (3-State) 1998 Apr 20 8 AC CHARACTERISTICS (Continued) GND = 0V; tr = tf ≤ 2.5ns; CL = 50pF; RL = 1KΩ SYMBOL PARAMETER WAVEFORM CONDITION LIMITS –40 to +85 °C LIMITS –40 to +125 °C UNIT VCC(V) MIN TYP1 MAX MIN MAX Shift clock pulse 2.0 34 10 – 41 – tW Shift clock pulse width HIGH or LOW Figure 1 2.7 25 8 – 30 – ns width HIGH or LOW 3.0 to 3.6 20 62 – 24 – Storage clock pulse 2.0 34 7 – 41 – tW Storage clock pulse width HIGH or LOW Figure 2 2.7 25 5 – 30 – ns width HIGH or LOW 3.0 to 3.6 20 42 – 24 – Master reset pulse 2.0 34 10 – 41 – tW Master reset pulse width LOW Figure 5 2.7 25 8 – 30 – ns width LOW 3.0 to 3.6 20 62 – 24 – 1.2 – 40 – – – t Set-up time Figure 4 2.0 26 14 – 31 – ns tsu DS to SHCP Figure 4 2.7 19 10 – 23 – ns 3.0 to 3.6 15 82 – 18 – 1.2 – 40 – – – t Set-up time Figure 2 2.0 26 14 – 31 – ns tsu SHCP to STCP Figure 2 2.7 19 10 – 23 – ns 3.0 to 3.6 15 82 – 18 – 1.2 – –10 – – – th Hold time Figure 4 2.0 5 –4 – 5 – ns th DS to SHCP Figure 4 2.7 5 –3 – 5 – ns 3.0 to 3.6 5 –22 – 5 – 1.2 – –35 – – – t Removal time Figure 5 2.0 5 –12 – 5 – ns trem MR to SHCP Figure 5 2.7 5 –9 – 5 – ns 3.0 to 3.6 5 –72 – 5 – Maximum clock 2.0 14 40 – 12 – fmax Maximum clock pulse frequency SH ST Figure 1, 2 2.7 19 58 – 16 – MHz SHCP or STCP 3.0 to 3.6 24 702 – 20 – NOTES: 1. Unless otherwise stated, all typical values are at Tamb = 25°C. 2. Typical value measured at VCC = 3.3V. |
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