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74LVC543A Datenblatt(PDF) 2 Page - NXP Semiconductors

Teilenummer 74LVC543A
Bauteilbeschribung  Octal D-type registered transceiver 3-State
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Hersteller  PHILIPS [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

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Philips Semiconductors
Product specification
74LVC543A
Octal D-type registered transceiver (3-State)
2
1998 Jul 31
853-1992 19813
FEATURES
5-volt tolerant inputs/outputs, for interfacing with 5-volt logic
Supply voltage range of 1.2V to 3.6V
Complies with JEDEC standard no. 8–1A
CMOS low power consumption
Direct interface with TTL levels
8-bit octal transceiver with D-type latch
Back-to-back registers for storage
Separate controls for data flow in each direction
3-State non-inverting outputs for bus oriented applications
High impedance when V
CC = 0V
DESCRIPTION
The 74LVC543A is a high–performance, low–power, low–voltage,
Si–gate CMOS device and superior to most advanced CMOS
compatible TTL families.
The 74LVC543A is an octal registered transceiver containing two
sets of D–type latches for temporary storage of the data flow in
either direction. Separate latch enable (LEAB, LEBA) and output
enable (OEAB, OEBA) inputs are provided for each register to permit
independent control of inputting and outputting in either direction of
the data flow.
The 74LVC543A contains eight D–type latches, with separate inputs
and controls for each set. For data flow from A to B, for example, the
A–to–B enable (EAB) input must be LOW in order to enter data from
A0–A7 or take data from B0–B7, as indicated in the function table.
With EAB LOW, a LOW signal on the A–to–B latch enable (LEAB)
input makes the A–to–B latches transparent; a subsequent LOW–to
HIGH transition of the LEAB signal puts the A data into the latches
where it is stored and the B outputs no longer change with the A
inputs. With EAB and OEAB both low, the 3–state B output buffers
are active and display the data present at the outputs of the A
latches
QUICK REFERENCE DATA
GND = 0V; Tamb = 25°C; Tr = Tf ≤ 2.5ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
tPHL/tPLH
Propagation delay
An to Bn
CL = 50 pF
VCC = 3.3V
3.3
ns
CI
input capacitance
5.0
pF
CI/O
input/output capacitance
10.0
pF
CPD
power dissipation capacitance per latch
VCC = 3.3V
27
pF
NOTES:
1. CPD is used to determine the dynamic power dissipation (PD in µW)
PD = CPD x VCC2 x fi +Σ (CL x VCC2 x fo ) where:
fi = input frequency in MHz; CL = output load capacity in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
Σ (CL x VCC2 x fo ) = sum of the outputs
2. The condition is VI = GND to VCC
ORDERING INFORMATION
PACKAGES
TEMPERATURE
RANGE
OUTSIDE NORTH
AMERICA
NORTH AMERICA
PKG DWG. #
24-Pin Plastic Small Outline (SO)
–40
°C to +85°C
74LVC543A D
74LVC543A D
SOT137-1
24-Pin Plastic Shrink Small Outline (SSOP) Type II
–40
°C to +85°C
74LVC543A DB
74LVC543A DB
SOT340-1
24-Pin Plastic Thin Shrink Small Outline (TSSOP) Type I
–40
°C to +85°C
74LVC543A PW
7LVC543APW DH
SOT355-1


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