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74LVC544A Datenblatt(PDF) 2 Page - NXP Semiconductors

Teilenummer 74LVC544A
Bauteilbeschribung  Octal D-type registered transceiver, inverting 3-State
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Hersteller  PHILIPS [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

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Philips Semiconductors
Product specification
74LVC544A
Octal D-type registered transceiver, inverting
(3-State)
2
1998 Jul 29
853-2107 19804
FEATURES
Wide supply voltage range of 1.2V to 3.6V
In accordance with JEDEC standard no. 8-1A
CMOS low power consumption
Direct interface with TTL levels
Combines 74LVC640 and 74LVC533 type functions in one chip
Octal transceiver with D-type latch
Back-to-back registers for storage
Separate controls for data flow in each direction
3-State inverting outputs for bus oriented applications
5 Volt tolerant inputs/outputs, for interfacing with 5 Volt logic
DESCRIPTION
The 74LVC544A is a high performance, low-power, low-voltage
Si-gate CMOS device and superior to most advanced CMOS
compatible TTL families.
Inputs can be driven from either 3.3V or 5.0V devices. In 3-State
operation, outputs can handle 5V. This feature allows the use of
these devices as translators in a mixed 3.3V/5V environment.
The 74LVC544A is an octal registered inverting transceiver
containing two sets of D-type latches for temporary storage of the
data flow in either direction. Separate latch enable (LEAB, LEBA)
and output enable (OEAB, OEBA) inputs are provided for each
register to permit independent control of inputting and outputting in
either direction of the data flow.
The ‘544A’ contains eight D-type latches with separate inputs and
controls for each set. For data flow from A to B, for example, the
A-to-B enable (EAB) input must be LOW in order to enter data from
A0–A7 or take data from B0–B7, as indicated in the function table.
With EAB LOW, a LOW signal on the A-to-B latch enable (LEAB)
input makes the A-to-B latches transparent; a subsequent
LOW-to-HIGH transition of the LEAB signal puts the A data into the
latches where it is stored and the B outputs no longer change with
the A inputs. With EAB and OEAB both LOW, the 3-State B output
buffers are active and display the data present at the outputs of the
A latches.
QUICK REFERENCE DATA
GND = 0V; Tamb = 25°C; tr = tf v2.5 ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
tPHL/tPLH
Propagation delay
An to Bn
CL = 50pF
VCC = 3.3V
4
ns
CI
Input capacitance
5.0
pF
CI/O
Input/output capacitance
10
pF
CPD
Power dissipation capacitance per latch
Notes 1, 2
30
pF
NOTES:
1. CPD is used to determine the dynamic power dissipation (PD in µW)
PD = CPD
VCC2 x fi )Σ (CL
VCC2
fo) where:
fi = input frequency in MHz; CL = output load capacitance in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
Σ (CL
VCC2
fo) = sum of the outputs.
2. The condition is VI = GND to VCC.
ORDERING AND PACKAGE INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH
AMERICA
NORTH AMERICA
PKG. DWG. #
24-Pin Plastic SO
–40
°C to +85°C
74LVC544A D
74LVC544A D
SOT137-1
24-Pin Plastic SSOP Type II
–40
°C to +85°C
74LVC544A DB
74LVC544A DB
SOT340-1
24-Pin Plastic TSSOP Type I
–40
°C to +85°C
74LVC544A PW
7LVC544APW DH
SOT355-1


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