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MC145484 Datenblatt(PDF) 7 Page - Motorola, Inc |
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MC145484 Datenblatt(HTML) 7 Page - Motorola, Inc |
7 / 26 page MC145484 MOTOROLA 7 Figure 2a. Long Frame Sync (Transmit and Receive Have Individual Clocking) Figure 2b. Short Frame Sync (Transmit and Receive Have Individual Clocking) Figure 2c. IDL Interface — BCLKR = 1 (Transmit and Receive Have Common Clocking) Figure 2d. GCI Interface — BCLKR = 0 (Transmit and Receive Have Common Clocking) Din (DR) IDL RX (DR) DON’T CARE DON’T CARE 8 DR 8 7 6 5 4 3 2 1 DR DON’T CARE DON’T CARE 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 B2–CHANNEL (FSR = 1) B1–CHANNEL (FSR = 0) B2–CHANNEL (FSR = 1) B1–CHANNEL (FSR = 0) Dout (DT) DCL (BCLKT) FSC (FST) IDL TX (DT) IDL CLOCK (BCLKT) IDL SYNC (FST) DT BCLKT (BCLKR) FST (FSR) DT BCLKT (BCLKR) FST (FSR) DON’T CARE DON’T CARE DON’T CARE DON’T CARE DON’T CARE 7 6 5 4 3 2 1 8 8 7 6 5 4 3 2 1 7 6 5 4 3 2 1 8 8 7 6 5 4 3 2 1 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 Figure 2. Digital Timing Modes for the PCM Data Interface |
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