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ADC0820 Datenblatt(PDF) 5 Page - NXP Semiconductors

Teilenummer ADC0820
Bauteilbeschribung  8-Bit, high-speed, mP-compatible A/D converter with track/hold function
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Hersteller  PHILIPS [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

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Philips Semiconductors Linear Products
Product specification
ADC0820
8-Bit, high-speed,
µP-compatible A/D converter with
track/hold function
August 31, 1994
572
AC ELECTRICAL CHARACTERISTICS
VDD = 5V, tR = tF = 20ns, VREF(+) = 5V, VREF(-) = 0V, and TA = 25°C, unless otherwise specified.
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS4
UNIT
SYMBOL
PARAMETER
TEST CONDITIONS
Min
Typ3
Max
UNIT
tCRD
Conversion time for RD mode
Mode=0, Figure 1
1.6
2.5
µs
tACCO
Access time (delay from falling edge of
RD to output valid)
Mode=0, Figure 1
tCRD+20
tCRD+50
ns
tCWR-RD
Conversion time for WR-RD mode
Mode=VDD, tWR=600ns, tRD=600ns;
Figures 3a and 3b
1.52
µs
tWR
Write time
Min
Mode=VDD, Figures 3a and 3b2
600
ns
tWR
Write time
Max
Mode=VDD, Figures 3a and 3b2
50
µs
tRD
Read time
Min
Mode=VDD, Figures 3a and 3b2
600
ns
tACC1
Access time (delay from falling edge of
RD t o output valid)
Mode=VDD, tRD<tI;
Figure 3b, CL=15pF
190
280
ns
tACC1
RD t o output valid)
CL=100pF
210
320
ns
tACC2
Access time (delay from falling edge of
RD t o output valid)
Mode=VDD, tRD>tI;
Figure 3a, CL=15pF
70
120
ns
CL=100pF
90
150
ns
tI
Internal comparison time
Mode=VDD;
Figures 2 and 3a, CL=50pF
800
1300
ns
t1H, t0H
Three-state control (delay from rising
edge of RD to Hi-Z state)
RL=1kΩ, CL=10pF
100
200
ns
tINTL
Delay from rising edge of WR to falling
edge of INT
Mode=VDD, CL=50pF
tRD>tI; Figure 3a
tRD<tI; Figure 3b
tRD+200
tI
tRD+290
ns
ns
tINTH
Delay from rising edge of RD to rising
edge of INT
Figures 1, 3a, and 3b,
CL=50pF
125
225
ns
tINTHWR
Delay from rising edge of WR to rising
edge of INT
Figure 2, CL=50pF
175
270
ns
tRDY
Delay from CS to RDY
Figure 1, CL=50pF, Mode=0
50
100
ns
tID
Delay from INT to output valid
Figure 2
20
50
ns
tRI
Delay from RD to INT
Mode=VDD, tRD<tI;
Figure 3b
200
290
ns
tP
Delay from end of conversion to next
conversion
Figures 1, 2, 3a, and 3b2
500
ns
SR
Slew rate, tracking
0.1
V/
µs
CVIN
Analog input capacitance
45
pF
COUT
Logic output capacitance
5
pF
CIN
Logic input capacitance
5
pF
NOTES:
1. Unadjusted error includes offset, full-scale, and linearity errors.
2. Accuracy may degrade if tWR or tRD is shorter than the minimum value specified.
3. Typical values are at 25
°C and represent most likely parametric norm.
4. Guaranteed but not 100% production tested. These limits are not used to calculate outgoing quality levels.
5. VREF and VIN must be applied after VCC has been turned on to prevent possibility of latching.


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