Philips Semiconductors Linear Products

Product specification

ADC0820

8-Bit, high-speed,

µP-compatible A/D converter with

track/hold function

August 31, 1994

577

before reading the conversion result. INT will typically go Low 800ns

after WR’s rising edge. However, if a shorter conversion time is

desired, the processor need not wait for INT and can exercise a

Read after only 600ns. If this is done, INT will immediately go Low

and data will appear at the outputs.

Stand-Alone (Figure 7)

For stand-alone operation in WR-RD mode, CS and RD can be tied

Low and a conversion can be started with WR. Data will be valid

approximately 800ns following WR’s rising edge.

Other Interface Considerations

In order to maintain conversion accuracy, WR has a maximum width

spec of 50

µs. When the MS flash ADC’s sampled data comparators

are in comparison mode (WR is Low), the input capacitors (C,

Figure 5) must hold their charge. Switch leakage can cause errors if

the comparator is left in this phase for too long.

Since the MS flash ADC enters its zeroing phase at the end of a

conversion, a new conversion cannot be started until this phase is

2, 3a, and 3b).

ANALOG CONSIDERATIONS

Reference and Input

the zero- to full-scale input range of the A/D converter. This allows

the designer to easily vary the span of the analog input since this

arrangement also facilitates ratiometric operation and, in many

cases, the chip power supply can be used for transducer power as

RD LOW

WR

CS LOW

INT

DB0–DB7

Figure 7. WR-RD Mode (Pin 7 is High)

Stand-Alone Operation

This reference flexibility lets the input span not only be varied, but

differential, the reference design affords nearly differential-input

capability for most measurement applications. Figure 9 shows some

of the configurations that are possible.

Input Current

Due to the unique conversion techniques employed by the

ADC0820, the analog input behaves somewhat differently than in

conventional devices. The A/D’s sampled data comparators take

varying amounts of input current depending on which cycle the

conversion is in.

The equivalent input circuit of the ADC0820 is shown in Figure 10a.

When a conversion starts (WR Low, WR-RD mode), all input

two 4-bit flash circuits are not both in their compare cycle at the

because the MS flash converter is connected to the input during its

compare interval and the LS flash is connected to the input during its

zero-phase input.

The input capacitors must charge to the input voltage through the on

resistance of the analog switches (about 5k

Ω to 10kΩ). In addition,

about 12pF of input stray capacitance must also be charged. For

large source resistances, the analog input can be modeled as an

longer for the input capacitance to charge.

In RD mode, the input switches are closed for approximately 800ns

at the start of the conversion. In WR-RD mode, the time that the

switches are closed to allow this charging is the time that WR is

Low. Since other factors force this time to be at least 600ns, input

time constants of 100ns can be accommodated without special

consideration. Typical total input capacitance values of 45pF allow

settle.

Input Filtering

It should be made clear that transients in the analog input signal,

A/D’s performance in most cases. In effect, the ADC0820 does not

“look” at the input when these transients occur. The comparators’

outputs are not latched while WR is Low, so at least 600ns will be

provided to charge the ADC’s input capacitance. It is