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TL16C752BTPTREP Datenblatt(PDF) 4 Page - Texas Instruments |
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TL16C752BTPTREP Datenblatt(HTML) 4 Page - Texas Instruments |
4 / 35 page TL16C752B-EP 3.3-V DUAL UART WITH 64-BYTE FIFO SGLS153 – FEBRUARY 2003 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 functional block diagram Control Signals Modem Control Signals Divisor Bus Interface Control and Status Block Status Signals Control Signals Status Signals Baud Rate Generator UART_CLK Receiver Block Logic Receiver FIFO 64-Byte Vote Logic Transmitter Block Logic Transmitter FIFO 64-Byte RX RX TX TX NOTE: The vote logic determines whether the RX data is a logic 1 or 0. It takes three samples of the RX line and uses a majority vote to determine the logic level received. The vote logic operates on all bits received. functional description The TL16C752B-EP UART is pin-compatible with the ST16C2550 UART. It provides more enhanced features. All additional features are provided through a special enhanced feature register. The UART performs a serial-to-parallel conversion on data characters received from peripheral devices or modems and parallel-to-parallel conversion on data characters transmitted by the processor. The complete status of each channel of the TL16C752B-EP UART can be read at any time during functional operation by the processor. The TL16C752B-EP can be placed in an alternate mode (FIFO mode) relieving the processor of excessive software overhead by buffering received/transmitted characters. Both the receiver and transmitter FIFOs can store up to 64 bytes (including three additional bits of error status per byte for the receiver FIFO) and have selectable or programmable trigger levels. Primary outputs RXRDY and TXRDY allow signalling of DMA transfers. The TL16C752B-EP has selectable hardware flow control and software flow control. Hardware flow control significantly reduces software overhead and increases system efficiency by automatically controlling serial data flow using the RTS output and CTS input signals. Software flow control automatically controls data flow by using programmable Xon/Xoff characters. The UART includes a programmable baud rate generator that can divide the timing reference clock input by a divisor between 1 and (216–1). |
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