MAY 1998 - REVISED FEBRUARY 2005

Specifications are subject to change without notice.

Customers should verify actual device performance in their specific applications.

TISP8200M & TISP8201M

The negative protection voltage, V(BO), will be the sum of the gate supply (VBATH) and the TISP8200M peak gate(terminal)-cathode voltage

(VGT). Under a.c. overvoltage conditions VGT will be less than 2.0 V. The integrated transistor buffer in the TISP8200M greatly reduces

protector’s source and sink current loading on the VBATH supply. Without the transistor, the SCR gate current would charge the VBATH supply.

An electronic power supply is not usually designed to be charged like a battery. As a result, the electronic supply would switch off and the SCR

gate current would provide the SLIC supply current. Normally the SLIC current would be less than the gate current, which would cause the

supply voltage to increase and destroy the SLIC by a supply overvoltage. Older designs using just SCRs needed to incorporate a sacrificial

zener diode across the supply line to go short if the supply voltage increased too much. The integrated transistor buffer removes the charging

problem and the need for a safety zener.

Fast rising impulses will cause short term overshoots in gate-cathode voltage. The negative protection voltage under impulse conditions will

also be increased if there is a long connection between the gate decoupling capacitor, C1, and the gate terminal. During the initial rise of a fast

impulse, the gate current (IG) is the same as the cathode current (IK). Rates of 60 A/µs can cause inductive voltages of 0.6 V in 2.5 cm of

printed wiring track. To minimize this inductive voltage increase of protection voltage, the length of the capacitor to gate terminal tracking

should be minimized.

The TISP8201M (buffered) gate is connected to the positive SLIC battery feed voltage (VBATR) to provide the protection reference voltage.

Positive overvoltages are initially clipped close to the SLIC positive supply rail value (VBATR) by the conduction of the TISP8201M transistor

base-emitter and the SCR gate-anode junctions. If sufficient current is available from the overvoltage, then the SCR will crowbar into a low

voltage ground referenced on-state condition. As the overvoltage subsides the SLIC pulls the conductor voltage down to its normal negative

value and this commutates the conducting SCR into a reverse biassed condition.

Operation of Gated Protectors (Continued)

Voltage Stress Levels on the TISP8200M and TISP8201M

Figure 6 shows the protector electrodes. The package terminal designated gate, G, is the transistor base, B, electrode connection and so is

marked as B (G). The following junctions are subject to voltage stress: Transistor EB and CB, SCR AK (reverse and off state). This clause

covers the necessary testing to ensure the junctions are good.

Testing transistor EB and SCR AK reverse: The highest reverse EB voltage and reverse AK voltage occurs during the overshoot period of the

other protector. For the TISP8200M, the SCR has VBATR plus the TISP8201M overshoot above VBATR. The transistor EB has an additional

VBATH voltage applied (see Figure 7). The reverse current, IR, flowing into the K terminal will be the sum of the transistor IEB and the actual

internal SCR IR . The reverse voltage applied to the K terminal is the TISP8201M protection voltage, V(BO) (VBATR plus overshoot), and the G

terminal has VBATH. Similarly for the TISP8201M, IR is measured with the TISP8200M V(BO) applied and it is the sum of the transistor IEB and

the actual internal SCR IR. VBATR is applied to the G terminal.

Figure 5. Overvoltage Conditions

C1

100 nF

I

G

SLIC

V

BATH

TISP

8200M

I

K

C2

100 nF

V

BATR

0 V

0 V

I

G

I

A

RING

TIP

AI8XAD

TISP

8201M